OpenSTA/verilog/test/verilog_remove_hier_buf.vok

module network_hier_test (clk,
    in1,
    in2,
    in3,
    out1,
    out2);
 input clk;
 input in1;
 input in2;
 input in3;
 output out1;
 output out2;

 wire w1;
 wire w2;
 wire w3;
 wire w4;
 wire w5;

 BUF_X2 buf_out1 (.A(w5),
    .Z(out1));
 INV_X1 inv1 (.A(w3),
    .ZN(w4));
 DFF_X1 reg1 (.D(w4),
    .CK(clk),
    .Q(w5));
 sub_block sub1 (.A(w1),
    .B(in2),
    .Y(w2));
 sub_block sub2 (.A(w2),
    .B(in3),
    .Y(w3));
endmodule
module sub_block (A,
    B,
    Y);
 input A;
 input B;
 output Y;

 wire n1;

 AND2_X1 and_gate (.A1(A),
    .A2(B),
    .ZN(n1));
endmodule