37 lines
1.1 KiB
Plaintext
37 lines
1.1 KiB
Plaintext
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time 1ns
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capacitance 1pF
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resistance 1kohm
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voltage 1v
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current 1mA
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power 1nW
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distance 1um
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Startpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r2/CK (DFF_X1)
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0.08 0.08 v r2/Q (DFF_X1)
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0.02 0.10 v u1/Z (BUF_X1)
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0.03 0.13 v u2/ZN (AND2_X1)
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0.00 0.13 v r3/D (DFF_X1)
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0.13 data arrival time
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10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ r3/CK (DFF_X1)
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-0.04 9.96 library setup time
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9.96 data required time
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---------------------------------------------------------
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9.96 data required time
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-0.13 data arrival time
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---------------------------------------------------------
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9.83 slack (MET)
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