OpenSTA/network/test/network_traversal.ok

--- get_fanin -to output pin -flat ---
fanin flat pin count: 3
--- get_fanin -to output pin -only_cells ---
fanin cells count: 2
--- get_fanin -to output pin -startpoints_only ---
fanin startpoints count: 1
--- get_fanout -from input pin -flat ---
fanout flat pin count: 6
--- get_fanout -from input pin -only_cells ---
fanout cells count: 4
--- get_fanout -from input pin -endpoints_only ---
fanout endpoints count: 1
--- get_fanin with -trace_arcs timing ---
fanin timing trace count: 3
--- get_fanin with -trace_arcs enabled ---
fanin enabled trace count: 3
--- get_fanin with -trace_arcs all ---
fanin all trace count: 3
--- get_fanout with -trace_arcs all ---
fanout all trace count: 6
--- get_fanin with -levels ---
fanin levels=1 count: 3
--- get_fanin with -pin_levels ---
fanin pin_levels=2 count: 3
--- get_fanout with -levels ---
fanout levels=1 count: 3
--- get_fanout with -pin_levels ---
fanout pin_levels=2 count: 3
--- get_cells -hierarchical ---
hierarchical cells count: 3
--- get_nets -hierarchical ---
hierarchical nets count: 6
--- get_pins -hierarchical ---
hierarchical pins count: 11
--- report_instance buf1 ---
Instance buf1
 Cell: BUF_X1
 Library: NangateOpenCellLibrary
 Path cells: BUF_X1
 Input pins:
  A input in1
 Output pins:
  Z output n1
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
--- report_instance and1 ---
Instance and1
 Cell: AND2_X1
 Library: NangateOpenCellLibrary
 Path cells: AND2_X1
 Input pins:
  A1 input n1
  A2 input in2
 Output pins:
  ZN output n2
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
--- report_instance reg1 ---
Instance reg1
 Cell: DFF_X1
 Library: NangateOpenCellLibrary
 Path cells: DFF_X1
 Input pins:
  D input n2
  CK input clk
 Output pins:
  Q output out1
  QN output (unconnected)
 Other pins:
  VDD power (unconnected)
  VSS ground (unconnected)
  IQ internal (unconnected)
  IQN internal (unconnected)
--- report_net n1 ---
Net n1
 Pin capacitance: 0.87-0.92
 Wire capacitance: 0.00
 Total capacitance: 0.87-0.92
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 buf1/Z output (BUF_X1)

Load pins
 and1/A1 input (AND2_X1) 0.87-0.92

--- report_net n2 ---
Net n2
 Pin capacitance: 1.06-1.14
 Wire capacitance: 0.00
 Total capacitance: 1.06-1.14
 Number of drivers: 1
 Number of loads: 1
 Number of pins: 2

Driver pins
 and1/ZN output (AND2_X1)

Load pins
 reg1/D input (DFF_X1) 1.06-1.14

--- get_full_name / get_name for instances ---
buf1 full_name: buf1
buf1 name: buf1
--- get_full_name / get_name for nets ---
n1 full_name: n1
n1 name: n1
--- get_full_name / get_name for pins ---
buf1/A full_name: buf1/A
--- get_full_name / get_name for ports ---
in1 full_name: in1
in1 name: in1
--- all_inputs ---
all_inputs count: 3
--- all_outputs ---
all_outputs count: 1
--- all_clocks ---
all_clocks count: 1
--- get_ports -filter direction == input ---
input ports count: 3
--- get_cells -filter ref_name == BUF_X1 ---
BUF_X1 cells count: 1
--- get_cells -filter ref_name == AND2_X1 ---
AND2_X1 cells count: 1
--- get_cells -filter ref_name == DFF_X1 ---
DFF_X1 cells count: 1
--- report_checks to verify timing graph ---
Startpoint: in1 (input port clocked by clk)
Endpoint: reg1 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

  Delay    Time   Description
---------------------------------------------------------
   0.00    0.00   clock clk (rise edge)
   0.00    0.00   clock network delay (ideal)
   0.00    0.00 v input external delay
   0.00    0.00 v in1 (in)
   0.02    0.02 v buf1/Z (BUF_X1)
   0.02    0.05 v and1/ZN (AND2_X1)
   0.00    0.05 v reg1/D (DFF_X1)
           0.05   data arrival time

  10.00   10.00   clock clk (rise edge)
   0.00   10.00   clock network delay (ideal)
   0.00   10.00   clock reconvergence pessimism
          10.00 ^ reg1/CK (DFF_X1)
  -0.04    9.96   library setup time
           9.96   data required time
---------------------------------------------------------
           9.96   data required time
          -0.05   data arrival time
---------------------------------------------------------
           9.92   slack (MET)