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OpenSTA/network/test/network_sdc_query.ok

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test: Initial upload Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-13 11:19:09 +01:00
--- bus range queries ---
data_a[0:3] ports: 4
data_a[4:7] ports: 4
result[0:3] ports: 4
data_b[7:0] ports: 8
--- wildcard subscript queries ---
data_a[*] ports: 8
data_b[*] ports: 8
result[*] ports: 8
--- individual bit queries ---
data_a[0]: dir=input name=data_a[0]
data_a[1]: dir=input name=data_a[1]
data_a[3]: dir=input name=data_a[3]
data_a[5]: dir=input name=data_a[5]
data_a[7]: dir=input name=data_a[7]
data_b[0]: dir=input name=data_b[0]
data_b[1]: dir=input name=data_b[1]
data_b[3]: dir=input name=data_b[3]
data_b[5]: dir=input name=data_b[5]
data_b[7]: dir=input name=data_b[7]
result[0]: dir=output name=result[0]
result[1]: dir=output name=result[1]
result[3]: dir=output name=result[3]
result[5]: dir=output name=result[5]
result[7]: dir=output name=result[7]
--- scalar port queries ---
clk: clk dir=input
carry: carry dir=output
overflow: overflow dir=output
--- glob patterns on bus ports ---
data* ports: 16
all ports: 27
result* ports: 8
?arry ports: 1
--- pin queries on bus design ---
all flat pins: 98
hierarchical pins: 98
*/A pins: 10
*/Z pins: 10
*/ZN pins: 10
*/CK pins: 8
*/D pins: 8
*/Q pins: 8
buf_a* pins: 16
and* pins: 27
reg* pins: 48
--- net queries on bus design ---
all nets: 45
stage1* nets: 8
stage2* nets: 8
hierarchical nets: 45
--- cell queries on bus design ---
total cells: 28
buf* cells: 10
and* cells: 9
reg* cells: 8
or* cells: 1
BUF_X1 cells: 10
AND2_X1 cells: 9
DFF_X1 cells: 8
--- report_net on bus nets ---
Net stage1[0]
Pin capacitance: 0.87-0.92
Wire capacitance: 0.00
Total capacitance: 0.87-0.92
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
buf_a0/Z output (BUF_X1)
Load pins
and0/A1 input (AND2_X1) 0.87-0.92
report_net stage1[0]: done
Net stage2[0]
Pin capacitance: 1.06-1.14
Wire capacitance: 0.00
Total capacitance: 1.06-1.14
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
and0/ZN output (AND2_X1)
Load pins
reg0/D input (DFF_X1) 1.06-1.14
report_net stage2[0]: done
Net stage1[3]
Pin capacitance: 0.87-0.92
Wire capacitance: 0.00
Total capacitance: 0.87-0.92
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
buf_a3/Z output (BUF_X1)
Load pins
and3/A1 input (AND2_X1) 0.87-0.92
report_net stage1[3]: done
Net stage2[3]
Pin capacitance: 1.06-1.14
Wire capacitance: 0.00
Total capacitance: 1.06-1.14
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
and3/ZN output (AND2_X1)
Load pins
reg3/D input (DFF_X1) 1.06-1.14
report_net stage2[3]: done
Net stage1[7]
Pin capacitance: 0.87-0.92
Wire capacitance: 0.00
Total capacitance: 0.87-0.92
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
buf_a7/Z output (BUF_X1)
Load pins
and7/A1 input (AND2_X1) 0.87-0.92
report_net stage1[7]: done
Net stage2[7]
Pin capacitance: 2.73-3.01
Wire capacitance: 0.00
Total capacitance: 2.73-3.01
Number of drivers: 1
Number of loads: 3
Number of pins: 4
Driver pins
and7/ZN output (AND2_X1)
Load pins
and_ovfl/A1 input (AND2_X1) 0.87-0.92
or_carry/A1 input (OR2_X1) 0.79-0.95
reg7/D input (DFF_X1) 1.06-1.14
report_net stage2[7]: done
Net internal_carry
Pin capacitance: 0.88-0.97
Wire capacitance: 0.00
Total capacitance: 0.88-0.97
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
or_carry/ZN output (OR2_X1)
Load pins
buf_carry/A input (BUF_X1) 0.88-0.97
report_net internal_carry: done
Net internal_overflow
Pin capacitance: 0.88-0.97
Wire capacitance: 0.00
Total capacitance: 0.88-0.97
Number of drivers: 1
Number of loads: 1
Number of pins: 2
Driver pins
and_ovfl/ZN output (AND2_X1)
Load pins
buf_ovfl/A input (BUF_X1) 0.88-0.97
report_net internal_overflow: done
--- report_instance on bus cells ---
Instance buf_a0
Cell: BUF_X1
Library: NangateOpenCellLibrary
Path cells: BUF_X1
Input pins:
A input data_a[0]
Output pins:
Z output stage1[0]
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
report_instance buf_a0: done
Instance buf_a7
Cell: BUF_X1
Library: NangateOpenCellLibrary
Path cells: BUF_X1
Input pins:
A input data_a[7]
Output pins:
Z output stage1[7]
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
report_instance buf_a7: done
Instance and0
Cell: AND2_X1
Library: NangateOpenCellLibrary
Path cells: AND2_X1
Input pins:
A1 input stage1[0]
A2 input data_b[0]
Output pins:
ZN output stage2[0]
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
report_instance and0: done
Instance and7
Cell: AND2_X1
Library: NangateOpenCellLibrary
Path cells: AND2_X1
Input pins:
A1 input stage1[7]
A2 input data_b[7]
Output pins:
ZN output stage2[7]
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
report_instance and7: done
Instance reg0
Cell: DFF_X1
Library: NangateOpenCellLibrary
Path cells: DFF_X1
Input pins:
D input stage2[0]
CK input clk
Output pins:
Q output result[0]
QN output (unconnected)
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
test: Fix post-merge build errors and regolden .ok files After merging upstream changes, fix all build errors in C++ test files and regolden Tcl test golden files to match updated code output. Build fixes: - dcalc/test/cpp/TestDcalc.cc: Fix const char* loop iterations, use EXPECT_NEAR for uninitialized subnormal float comparison - liberty/test/cpp/TestLibertyStaBasicsB.cc: Wrap tests using removed LibertyBuilder() default constructor in #if 0 - liberty/test/cpp/TestLibertyStaCallbacks.cc: Fix LibertyBuilder() call to use sta_->debug()/report(); wrap old visitor tests in #if 0 - search/test/cpp/TestSearchStaDesignB.cc: Fix pg->name() nullptr comparison (now returns std::string&) - search/test/cpp/TestSearchStaInit.cc: Fix 5 clkPinsInvalid/isIdealClock tests to expect throw (API now requires linked network) Tcl test fixes: - Remove calls to removed APIs: report_path_end_header/footer, report_path_end2 from 6 search test scripts; regolden their .ok files - Regolden .ok files for liberty (15), graph (1), network (8), parasitics (3), sdc (3), util (2), verilog (8) modules to reflect upstream format changes (timing arcs output, pin ordering, spacing) All 6103 tests now pass. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-03-11 09:11:08 +01:00
IQ internal (unconnected)
IQN internal (unconnected)
test: Initial upload Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-13 11:19:09 +01:00
report_instance reg0: done
Instance reg7
Cell: DFF_X1
Library: NangateOpenCellLibrary
Path cells: DFF_X1
Input pins:
D input stage2[7]
CK input clk
Output pins:
Q output result[7]
QN output (unconnected)
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
test: Fix post-merge build errors and regolden .ok files After merging upstream changes, fix all build errors in C++ test files and regolden Tcl test golden files to match updated code output. Build fixes: - dcalc/test/cpp/TestDcalc.cc: Fix const char* loop iterations, use EXPECT_NEAR for uninitialized subnormal float comparison - liberty/test/cpp/TestLibertyStaBasicsB.cc: Wrap tests using removed LibertyBuilder() default constructor in #if 0 - liberty/test/cpp/TestLibertyStaCallbacks.cc: Fix LibertyBuilder() call to use sta_->debug()/report(); wrap old visitor tests in #if 0 - search/test/cpp/TestSearchStaDesignB.cc: Fix pg->name() nullptr comparison (now returns std::string&) - search/test/cpp/TestSearchStaInit.cc: Fix 5 clkPinsInvalid/isIdealClock tests to expect throw (API now requires linked network) Tcl test fixes: - Remove calls to removed APIs: report_path_end_header/footer, report_path_end2 from 6 search test scripts; regolden their .ok files - Regolden .ok files for liberty (15), graph (1), network (8), parasitics (3), sdc (3), util (2), verilog (8) modules to reflect upstream format changes (timing arcs output, pin ordering, spacing) All 6103 tests now pass. Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-03-11 09:11:08 +01:00
IQ internal (unconnected)
IQN internal (unconnected)
test: Initial upload Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-13 11:19:09 +01:00
report_instance reg7: done
Instance or_carry
Cell: OR2_X1
Library: NangateOpenCellLibrary
Path cells: OR2_X1
Input pins:
A1 input stage2[7]
A2 input stage2[6]
Output pins:
ZN output internal_carry
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
report_instance or_carry: done
Instance and_ovfl
Cell: AND2_X1
Library: NangateOpenCellLibrary
Path cells: AND2_X1
Input pins:
A1 input stage2[7]
A2 input stage2[6]
Output pins:
ZN output internal_overflow
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
report_instance and_ovfl: done
Instance buf_carry
Cell: BUF_X1
Library: NangateOpenCellLibrary
Path cells: BUF_X1
Input pins:
A input internal_carry
Output pins:
Z output carry
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
report_instance buf_carry: done
Instance buf_ovfl
Cell: BUF_X1
Library: NangateOpenCellLibrary
Path cells: BUF_X1
Input pins:
A input internal_overflow
Output pins:
Z output overflow
Other pins:
VDD power (unconnected)
VSS ground (unconnected)
report_instance buf_ovfl: done
--- liberty library queries ---
libraries: 1
all lib cells: 134
NAND* lib cells: 9
NOR* lib cells: 9
MUX* lib cells: 2
DFF* lib cells: 8
AOI* lib cells: 15
OAI* lib cells: 16
--- registers in bus design ---
all_registers: 8
register data_pins: 8
register clock_pins: 8
register output_pins: 16
--- timing analysis ---
Startpoint: data_a[6] (input port clocked by clk)
Endpoint: carry (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[6] (in)
0.06 0.06 v buf_a6/Z (BUF_X1)
0.03 0.09 v and6/ZN (AND2_X1)
0.05 0.13 v or_carry/ZN (OR2_X1)
0.02 0.16 v buf_carry/Z (BUF_X1)
0.00 0.16 v carry (out)
0.16 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.16 data arrival time
---------------------------------------------------------
9.84 slack (MET)
Startpoint: data_b[0] (input port clocked by clk)
Endpoint: reg0 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 ^ data_b[0] (in)
0.04 0.04 ^ and0/ZN (AND2_X1)
0.00 0.04 ^ reg0/D (DFF_X1)
0.04 data arrival time
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ reg0/CK (DFF_X1)
0.01 0.01 library hold time
0.01 data required time
---------------------------------------------------------
0.01 data required time
-0.04 data arrival time
---------------------------------------------------------
0.04 slack (MET)
No paths found.
No paths found.
Startpoint: data_a[7] (input port clocked by clk)
Endpoint: carry (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[7] (in)
0.06 0.06 v buf_a7/Z (BUF_X1)
0.03 0.09 v and7/ZN (AND2_X1)
0.04 0.13 v or_carry/ZN (OR2_X1)
0.02 0.15 v buf_carry/Z (BUF_X1)
0.00 0.15 v carry (out)
0.15 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.15 data arrival time
---------------------------------------------------------
9.85 slack (MET)
Startpoint: data_b[6] (input port clocked by clk)
Endpoint: overflow (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_b[6] (in)
0.07 0.07 v and6/ZN (AND2_X1)
0.03 0.10 v and_ovfl/ZN (AND2_X1)
0.02 0.12 v buf_ovfl/Z (BUF_X1)
0.00 0.12 v overflow (out)
0.12 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.12 data arrival time
---------------------------------------------------------
9.88 slack (MET)
Merge upstream STA update and adapt all tests to new API Major upstream refactoring: Corner→Scene, Mode architecture, warning format change (Warning ID:), command renames, and many API signature changes. Adapted all C++ test files and TCL test scripts/expected output files to pass with the new API. 6159/6159 tests pass. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 15:05:29 +01:00
Warning 168: network_sdc_query.tcl line 1, unknown field nets.
test: Initial upload Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-13 11:19:09 +01:00
Startpoint: data_a[6] (input port clocked by clk)
Endpoint: carry (output port clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
1 0.88 0.10 0.00 0.00 v data_a[6] (in)
0.10 0.00 0.00 v buf_a6/A (BUF_X1)
1 0.87 0.01 0.06 0.06 v buf_a6/Z (BUF_X1)
0.01 0.00 0.06 v and6/A1 (AND2_X1)
3 2.85 0.01 0.03 0.09 v and6/ZN (AND2_X1)
0.01 0.00 0.09 v or_carry/A2 (OR2_X1)
1 0.88 0.01 0.05 0.13 v or_carry/ZN (OR2_X1)
0.01 0.00 0.13 v buf_carry/A (BUF_X1)
1 0.00 0.00 0.02 0.16 v buf_carry/Z (BUF_X1)
0.00 0.00 0.16 v carry (out)
0.16 data arrival time
0.00 10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
-----------------------------------------------------------------------------
10.00 data required time
-0.16 data arrival time
-----------------------------------------------------------------------------
9.84 slack (MET)
Merge upstream STA update and adapt all tests to new API Major upstream refactoring: Corner→Scene, Mode architecture, warning format change (Warning ID:), command renames, and many API signature changes. Adapted all C++ test files and TCL test scripts/expected output files to pass with the new API. 6159/6159 tests pass. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 15:05:29 +01:00
Warning 502: network_sdc_query.tcl line 1, report_checks -endpoint_count is deprecated. Use -endpoint_path_count instead.
test: Initial upload Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-13 11:19:09 +01:00
Startpoint: data_a[6] (input port clocked by clk)
Endpoint: carry (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[6] (in)
0.06 0.06 v buf_a6/Z (BUF_X1)
0.03 0.09 v and6/ZN (AND2_X1)
0.05 0.13 v or_carry/ZN (OR2_X1)
0.02 0.16 v buf_carry/Z (BUF_X1)
0.00 0.16 v carry (out)
0.16 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.16 data arrival time
---------------------------------------------------------
9.84 slack (MET)
Startpoint: data_a[7] (input port clocked by clk)
Endpoint: carry (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[7] (in)
0.06 0.06 v buf_a7/Z (BUF_X1)
0.03 0.09 v and7/ZN (AND2_X1)
0.04 0.13 v or_carry/ZN (OR2_X1)
0.02 0.15 v buf_carry/Z (BUF_X1)
0.00 0.15 v carry (out)
0.15 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.15 data arrival time
---------------------------------------------------------
9.85 slack (MET)
Startpoint: data_b[6] (input port clocked by clk)
Endpoint: carry (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_b[6] (in)
0.07 0.07 v and6/ZN (AND2_X1)
0.05 0.12 v or_carry/ZN (OR2_X1)
0.02 0.14 v buf_carry/Z (BUF_X1)
0.00 0.14 v carry (out)
0.14 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.14 data arrival time
---------------------------------------------------------
9.86 slack (MET)
Startpoint: data_a[6] (input port clocked by clk)
Endpoint: overflow (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[6] (in)
0.06 0.06 v buf_a6/Z (BUF_X1)
0.03 0.09 v and6/ZN (AND2_X1)
0.03 0.12 v and_ovfl/ZN (AND2_X1)
0.02 0.14 v buf_ovfl/Z (BUF_X1)
0.00 0.14 v overflow (out)
0.14 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.14 data arrival time
---------------------------------------------------------
9.86 slack (MET)
Startpoint: data_a[7] (input port clocked by clk)
Endpoint: overflow (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[7] (in)
0.06 0.06 v buf_a7/Z (BUF_X1)
0.03 0.09 v and7/ZN (AND2_X1)
0.03 0.11 v and_ovfl/ZN (AND2_X1)
0.02 0.14 v buf_ovfl/Z (BUF_X1)
0.00 0.14 v overflow (out)
0.14 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.14 data arrival time
---------------------------------------------------------
9.86 slack (MET)
Merge upstream STA update and adapt all tests to new API Major upstream refactoring: Corner→Scene, Mode architecture, warning format change (Warning ID:), command renames, and many API signature changes. Adapted all C++ test files and TCL test scripts/expected output files to pass with the new API. 6159/6159 tests pass. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com> Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-23 15:05:29 +01:00
Warning 503: network_sdc_query.tcl line 1, report_checks -group_count is deprecated. Use -group_path_count instead.
test: Initial upload Signed-off-by: Jaehyun Kim <jhkim@precisioninno.com>
2026-02-13 11:19:09 +01:00
Startpoint: data_a[6] (input port clocked by clk)
Endpoint: carry (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[6] (in)
0.06 0.06 v buf_a6/Z (BUF_X1)
0.03 0.09 v and6/ZN (AND2_X1)
0.05 0.13 v or_carry/ZN (OR2_X1)
0.02 0.16 v buf_carry/Z (BUF_X1)
0.00 0.16 v carry (out)
0.16 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.16 data arrival time
---------------------------------------------------------
9.84 slack (MET)
Startpoint: data_a[6] (input port clocked by clk)
Endpoint: overflow (output port clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[6] (in)
0.06 0.06 v buf_a6/Z (BUF_X1)
0.03 0.09 v and6/ZN (AND2_X1)
0.03 0.12 v and_ovfl/ZN (AND2_X1)
0.02 0.14 v buf_ovfl/Z (BUF_X1)
0.00 0.14 v overflow (out)
0.14 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
0.00 10.00 output external delay
10.00 data required time
---------------------------------------------------------
10.00 data required time
-0.14 data arrival time
---------------------------------------------------------
9.86 slack (MET)
Startpoint: data_a[6] (input port clocked by clk)
Endpoint: reg6 (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Delay Time Description
---------------------------------------------------------
0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 v input external delay
0.00 0.00 v data_a[6] (in)
0.06 0.06 v buf_a6/Z (BUF_X1)
0.03 0.09 v and6/ZN (AND2_X1)
0.00 0.09 v reg6/D (DFF_X1)
0.09 data arrival time
10.00 10.00 clock clk (rise edge)
0.00 10.00 clock network delay (ideal)
0.00 10.00 clock reconvergence pessimism
10.00 ^ reg6/CK (DFF_X1)
-0.04 9.96 library setup time
9.96 data required time
---------------------------------------------------------
9.96 data required time
-0.09 data arrival time
---------------------------------------------------------
9.87 slack (MET)