29 lines
1.5 KiB
Plaintext
29 lines
1.5 KiB
Plaintext
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Startpoint: in (input port clocked by clk)
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Endpoint: _1415_ (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Cap Slew Delay Time Description Src Attr
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---------------------------------------------------------------------------------------------------------------
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0.00 0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 v input external delay
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0.00 0.00 0.00 0.00 v in (in)
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in (net)
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0.00 0.00 0.00 v _1415_/D (sky130_fd_sc_hd__dfrtp_1) synthesis/tests/counter.v:22.3-28.6
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0.00 data arrival time
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0.00 10.00 10.00 clock clk (rise edge)
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0.00 10.00 clock network delay (ideal)
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0.00 10.00 clock reconvergence pessimism
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10.00 ^ _1415_/CLK (sky130_fd_sc_hd__dfrtp_1)
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-0.10 9.90 library setup time
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9.90 data required time
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---------------------------------------------------------------------------------------------------------------
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9.90 data required time
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-0.00 data arrival time
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---------------------------------------------------------------------------------------------------------------
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9.90 slack (MET)
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