88 lines
3.1 KiB
Plaintext
88 lines
3.1 KiB
Plaintext
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Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r4 (rising edge-triggered flip-flop clocked by clk)
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Path Group: long
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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64.76 64.76 ^ r1/Q (DFFHQx4_ASAP7_75t_R)
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17.77 82.53 ^ u2/Y (BUFx2_ASAP7_75t_R)
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17.88 100.42 ^ u3/Y (BUFx2_ASAP7_75t_R)
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16.66 117.08 ^ u4/Y (BUFx2_ASAP7_75t_R)
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0.00 117.08 ^ r4/D (DFFHQx4_ASAP7_75t_R)
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117.08 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r4/CLK (DFFHQx4_ASAP7_75t_R)
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-12.61 487.39 library setup time
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487.39 data required time
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---------------------------------------------------------
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487.39 data required time
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-117.08 data arrival time
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---------------------------------------------------------
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370.32 slack (MET)
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Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r3 (rising edge-triggered flip-flop clocked by clk)
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Path Group: custom
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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64.76 64.76 ^ r1/Q (DFFHQx4_ASAP7_75t_R)
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17.77 82.53 ^ u2/Y (BUFx2_ASAP7_75t_R)
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17.88 100.42 ^ u3/Y (BUFx2_ASAP7_75t_R)
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0.00 100.42 ^ r3/D (DFFHQx4_ASAP7_75t_R)
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100.42 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r3/CLK (DFFHQx4_ASAP7_75t_R)
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-12.98 487.02 library setup time
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487.02 data required time
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---------------------------------------------------------
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487.02 data required time
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-100.42 data arrival time
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---------------------------------------------------------
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386.60 slack (MET)
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Startpoint: r1 (rising edge-triggered flip-flop clocked by clk)
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Endpoint: r2 (rising edge-triggered flip-flop clocked by clk)
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Path Group: clk
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Path Type: max
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Delay Time Description
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---------------------------------------------------------
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0.00 0.00 clock clk (rise edge)
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0.00 0.00 clock network delay (ideal)
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0.00 0.00 ^ r1/CLK (DFFHQx4_ASAP7_75t_R)
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64.76 64.76 ^ r1/Q (DFFHQx4_ASAP7_75t_R)
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17.77 82.53 ^ u2/Y (BUFx2_ASAP7_75t_R)
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0.00 82.53 ^ r2/D (DFFHQx4_ASAP7_75t_R)
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82.53 data arrival time
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500.00 500.00 clock clk (rise edge)
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0.00 500.00 clock network delay (ideal)
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0.00 500.00 clock reconvergence pessimism
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500.00 ^ r2/CLK (DFFHQx4_ASAP7_75t_R)
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-12.98 487.02 library setup time
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487.02 data required time
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---------------------------------------------------------
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487.02 data required time
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-82.53 data arrival time
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---------------------------------------------------------
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404.48 slack (MET)
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