53 lines
945 B
Plaintext
53 lines
945 B
Plaintext
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*SPEF "IEEE 1481-1998"
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*DESIGN "top"
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*DATE "2026"
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*VENDOR "OpenSTA test"
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*PROGRAM "hand written"
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*VERSION "1.0.1c"
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*DESIGN_FLOW "MISSING_NETS"
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*DIVIDER /
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*DELIMITER :
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*BUS_DELIMITER [ ]
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*T_UNIT 1.0 PS
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*C_UNIT 1.0 FF
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*R_UNIT 1.0 KOHM
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*L_UNIT 1.0 UH
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// Each buffer output net z<i> is degenerate two ways:
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// - z<i>:2 z<i>:3 have ground cap but NO resistor (floating islands)
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// - u<i>:Y -- z<i>:1 is a 0 KOHM resistor (an ideal short)
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// Both used to make PrimaDelayCalc::primaReduce() factorize a singular G
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// (STA-1752). node_count_ = 5 > prima_order_ (default 3) selects the
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// primaReduce() path that factorizes the pure G matrix.
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*D_NET z0 40.2
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*CONN
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*I u0:Y O
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*I t0:D I *L .0086
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*CAP
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1 u0:Y 6.7
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2 t0:D 6.7
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3 z0:1 6.7
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4 z0:2 6.7
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5 z0:3 6.7
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*RES
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6 u0:Y z0:1 0
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7 z0:1 t0:D 2.42
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*END
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*D_NET z1 40.2
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*CONN
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*I u1:Y O
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*I t1:D I *L .0086
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*CAP
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1 u1:Y 6.7
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2 t1:D 6.7
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3 z1:1 6.7
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4 z1:2 6.7
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5 z1:3 6.7
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*RES
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6 u1:Y z1:1 0
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7 z1:1 t1:D 2.42
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*END
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