2018-09-28 17:54:21 +02:00
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// OpenSTA, Static Timing Analyzer
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2025-01-22 02:54:33 +01:00
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// Copyright (c) 2025, Parallax Software, Inc.
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2018-09-28 17:54:21 +02:00
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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2022-01-04 18:17:08 +01:00
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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2018-09-28 17:54:21 +02:00
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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2022-01-04 18:17:08 +01:00
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// along with this program. If not, see <https://www.gnu.org/licenses/>.
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2025-01-22 02:54:33 +01:00
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//
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// The origin of this software must not be misrepresented; you must not
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// claim that you wrote the original software.
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//
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// Altered source versions must be plainly marked as such, and must not be
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// misrepresented as being the original software.
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//
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// This notice may not be removed or altered from any source distribution.
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2018-09-28 17:54:21 +02:00
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2020-02-16 01:13:16 +01:00
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#pragma once
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2018-09-28 17:54:21 +02:00
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2020-04-05 23:53:44 +02:00
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#include "Map.hh"
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#include "NetworkClass.hh"
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#include "LibertyClass.hh"
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#include "SdcClass.hh"
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2018-09-28 17:54:21 +02:00
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namespace sta {
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class TimingRole;
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class DisabledCellPorts;
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class DisabledInstancePorts;
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typedef Vector<DisabledInstancePorts*> DisabledInstancePortsSeq;
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typedef Vector<DisabledCellPorts*> DisabledCellPortsSeq;
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2023-01-19 19:23:45 +01:00
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typedef Vector<LibertyPortPair> LibertyPortPairSeq;
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typedef Set<TimingArcSet*> TimingArcSetSet;
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// Base class for disabled cell and instance ports.
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class DisabledPorts
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{
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public:
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DisabledPorts();
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~DisabledPorts();
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void setDisabledAll();
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void removeDisabledAll();
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void setDisabledFrom(LibertyPort *port);
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void removeDisabledFrom(LibertyPort *port);
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void setDisabledTo(LibertyPort *port);
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void removeDisabledTo(LibertyPort *port);
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2022-06-03 19:00:04 +02:00
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void setDisabledFromTo(LibertyPort *from,
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LibertyPort *to);
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void removeDisabledFromTo(LibertyPort *from,
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LibertyPort *to);
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bool isDisabled(LibertyPort *from,
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LibertyPort *to,
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const TimingRole *role);
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LibertyPortPairSet *fromTo() const { return from_to_; }
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LibertyPortSet *from() const { return from_; }
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LibertyPortSet *to() const { return to_; }
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bool all() const { return all_; }
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private:
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bool all_;
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LibertyPortSet *from_;
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LibertyPortSet *to_;
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LibertyPortPairSet *from_to_;
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};
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// set_disable_timing cell [-from] [-to]
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class DisabledCellPorts : public DisabledPorts
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{
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public:
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DisabledCellPorts(LibertyCell *cell);
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~DisabledCellPorts();
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LibertyCell *cell() const { return cell_; }
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void setDisabled(TimingArcSet *arc_set);
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void removeDisabled(TimingArcSet *arc_set);
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bool isDisabled(TimingArcSet *arc_set) const;
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TimingArcSetSet *timingArcSets() const { return arc_sets_; }
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using DisabledPorts::isDisabled;
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private:
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LibertyCell *cell_;
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TimingArcSetSet *arc_sets_;
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};
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// set_disable_timing instance [-from] [-to]
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class DisabledInstancePorts : public DisabledPorts
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{
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public:
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DisabledInstancePorts(Instance *inst);
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Instance *instance() const { return inst_; }
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private:
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Instance *inst_;
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};
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2023-01-19 19:23:45 +01:00
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DisabledCellPortsSeq
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sortByName(DisabledCellPortsMap *cell_map);
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DisabledInstancePortsSeq
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sortByPathName(const DisabledInstancePortsMap *inst_map,
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const Network *network);
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LibertyPortPairSeq
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sortByName(const LibertyPortPairSet *set);
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2018-09-28 17:54:21 +02:00
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} // namespace
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