mirror of https://github.com/VLSIDA/OpenRAM.git
87 lines
3.5 KiB
Python
87 lines
3.5 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2024 Regents of the University of California, Santa Cruz
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# All rights reserved.
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#
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from openram.sram_factory import factory
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from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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from openram.base import geometry
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from .pattern import pattern
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class dummy_array(bitcell_base_array):
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"""
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Generate a dummy row/column for the replica array.
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"""
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def __init__(self, rows, cols, column_offset=0, row_offset=0 ,mirror=0, location="", name="", left_rbl=0, right_rbl=0):
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super().__init__(rows=rows, cols=cols, column_offset=column_offset, name=name)
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self.location = location
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self.row_offset = row_offset
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self.mirror = mirror
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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""" Create and connect the netlist """
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# This will create a default set of bitline/wordline names
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.add_modules()
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self.add_pins()
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self.create_instances()
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def create_layout(self):
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self.place_array()
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self.add_layout_pins()
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self.route_supplies()
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self.add_boundary()
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self.DRC_LVS()
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def add_modules(self):
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""" Add the modules used in this design """
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self.dummy_cell = factory.create(module_type=OPTS.dummy_bitcell)
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self.cell = factory.create(module_type=OPTS.bitcell)
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def create_instances(self):
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""" Create the module instances used in this design """
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self.cell_inst={}
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if self.cell.mirror.y:
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core_block = [[0 for x in range(2)] for y in range(2)]
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core_block[(0+self.mirror) %2][(0+self.column_offset+self.row_offset) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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core_block[(1+self.mirror) %2][(0+self.column_offset+self.row_offset) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True)
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core_block[(0+self.mirror) %2][(1+self.column_offset+self.row_offset) %2] = geometry.instance("core_0_1", mod=self.dummy_cell, is_bitcell=True, mirror='XY')
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core_block[(1+self.mirror) %2][(1+self.column_offset+self.row_offset) %2] = geometry.instance("core_1_1", mod=self.dummy_cell, is_bitcell=True, mirror='MY')
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else:
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core_block = [[0 for x in range(1)] for y in range(2)]
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core_block[(1+self.mirror) %2][(0+self.column_offset) %2] = geometry.instance("core_0_0", mod=self.dummy_cell, is_bitcell=True, mirror='MX')
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core_block[(0+self.mirror) %2][(0+self.column_offset) %2] = geometry.instance("core_1_0", mod=self.dummy_cell, is_bitcell=True)
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self.pattern = pattern(self, "dummy_array", core_block, num_rows=self.row_size, num_cols=self.column_size, name_template="bit_r{0}_c{1}")
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self.pattern.connect_array()
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def add_pins(self):
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# bitline pins are not added because they are floating
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for bl_name in self.get_bitline_names():
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self.add_pin(bl_name, "INOUT")
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# bitline pins are not added because they are floating
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for wl_name in self.get_wordline_names():
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self.add_pin(wl_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def input_load(self):
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# FIXME: This appears to be old code from previous characterization. Needs to be updated.
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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