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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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fcacd46866ed2ed9350f9306637878a9a227f236
OpenRAM/compiler/characterizer
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Matt Guthaus fcacd46866 UPdate tests with new delay and slew names and leakage power.
2018-02-21 15:45:49 -08:00
..
__init__.py
Fail simulation tests if correct spice is not found. Correctly load spice characterizer.
2018-01-26 13:00:25 -08:00
charutils.py
Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit.
2018-02-21 13:38:43 -08:00
delay.py
UPdate tests with new delay and slew names and leakage power.
2018-02-21 15:45:49 -08:00
lib.py
UPdate tests with new delay and slew names and leakage power.
2018-02-21 15:45:49 -08:00
setup_hold.py
Include leakage of non-trimmed array. Back out leakage of trimmed, add back leakage of nontrimmed. Reorgs simulation of delay and power a bit.
2018-02-21 13:38:43 -08:00
stimuli.py
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
2018-02-12 09:33:23 -08:00
trim_spice.py
Move delay-specific stimulus commands to delay.py. Keep stimuli.py generic.
2018-02-07 12:58:47 -08:00
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