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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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fbb2ea5fb697c1ef9fd604c2a1c9be3b871e37a8
OpenRAM/compiler/router
T
History
mrg b6c3580e24 Fix width of replica routes. Don't enclose pins if they overlap sufficiently.
2022-05-09 11:44:46 -07:00
..
direction.py
PEP8 cleanup
2021-02-23 13:32:13 -08:00
grid_cell.py
Add unblocking of source and destination pins to router.
2022-03-18 14:44:13 -07:00
grid_path.py
Update copyright year.
2021-01-22 11:23:28 -08:00
grid_utils.py
Update copyright year.
2021-01-22 11:23:28 -08:00
grid.py
Fix power ring routing boundary bug.
2022-03-18 10:32:25 -07:00
pin_group.py
Reimplement off grid pins.
2022-05-02 15:43:14 -07:00
router_tech.py
Add left stripe power routes to tree router as option.
2021-05-05 13:45:12 -07:00
router.py
Fix width of replica routes. Don't enclose pins if they overlap sufficiently.
2022-05-09 11:44:46 -07:00
signal_escape_router.py
Fix power ring routing boundary bug.
2022-03-18 10:32:25 -07:00
signal_grid.py
Fix power ring routing boundary bug.
2022-03-18 10:32:25 -07:00
signal_router.py
Add unblocking of source and destination pins to router.
2022-03-18 14:44:13 -07:00
supply_grid_router.py
Separate supply pin type from route supplies option
2021-05-28 11:55:50 -07:00
supply_grid.py
Update copyright year.
2021-01-22 11:23:28 -08:00
supply_tree_router.py
Remove debug output.
2022-05-02 16:42:04 -07:00
vector3d.py
Add dnwell
2021-05-26 16:14:16 -07:00
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