mirror of https://github.com/VLSIDA/OpenRAM.git
72 lines
2.4 KiB
Markdown
72 lines
2.4 KiB
Markdown
### [Go Back](./index.md#directory)
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# Base Data Structures
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This page of the documentation explains the base data structures of OpenRAM.
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## Table of Contents
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1. [Design Classes](#design-classes)
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2. [Base Class Inheritance](#base-class-inheritance)
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3. [Parameterized Transistor](#parameterized-transistor-ptx-or-pfinfet)
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4. [Parameterized Cells](#parameterized-cells)
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## Design Classes
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<img align="right" height="100" src="../assets/images/base_data_structures/layout_1.png">
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* SPICE and GDS2 Interfaces
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* Custom cells (read GDS and SPICE)
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* Generated cells (creates GDS and SPICE "on the fly")
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* Netlist functions
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* Add (directional) pins
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* Add and connect instances
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<img align="right" height="100" src="../assets/images/base_data_structures/layout_2.png">
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* Layout functions
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* Place instances
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* Add wires, routes, vias
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* Channel and Power router
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* Verification functions (wrap around DRC and LVS tools)
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## Base Class Inheritance
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```mermaid
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flowchart TD
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A[design.py \n\n General design and helper DRC constants] --> B[hierarchy_design.py \n\n DRC/LVS functions]
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B --> C["hierarchy_spice.py \n\n Netlist related functionality"]
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B --> D["hierarchy_layout.py \n\n Layout related functionality"]
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C --> E["Functions: \n add_pins \n add_inst"]
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C --> F["sp_read \n sp_write \n Power data \n Delay data"]
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D --> G["Functions: \n add_{layout_pin,rect,...} \n place_inst \n create_channel_route \n etc."]
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D --> H["gds_read \n gds_write \n get_blockages \n etc."]
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```
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## Parameterized Transistor (ptx or pfinfet)
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<img align="right" height="100" src="../assets/images/base_data_structures/transistor.png">
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* Creates variable size/finger nmos or pmos transistor
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* Optional gate and source/drain contacts in naive way
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* Not optimal layout, but "good enough"
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* Offset (0,0) is lower-left corner of active area
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* Size/fingers effect on size must be estimated elsewhere perhaps by trying configurations
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## Parameterized Cells
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<img align="right" height="230" src="../assets/images/base_data_structures/parameterized_cell.png">
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Dynamically generated cells (in `$OPENRAM_HOME/pgates`)
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* Not the most efficient layouts but "ok"
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* Try to use restrictive design rules to keep them portable
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* Transistors
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* `ptx`, `pfinfet`
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* Logic gates
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* `pinv`, `pnand2`, `pnand3`, `pnor2`
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* Buffer/drivers
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* `pbuf`, `pinvbuf`, `pdriver`
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* SRAM Logic
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* `precharge`, `single_level_column_mux` |