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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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fb2ed1d46c3d3993acb2d1b995e1ff8191158967
OpenRAM/technology
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Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
..
freepdk45
Remove dead code ptx_port.
2018-01-19 16:19:05 -08:00
scn3me_subm
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
setup_scripts
Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.
2018-01-19 16:38:19 -08:00
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