Bastian Koppelmann de6b207798 hierachy_layout: Move number of via arg to add_power_pins() ... this allows custom modules to state how many vias they need for power rails. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>		2019-12-18 17:33:43 +01:00
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contact.py	Clean up and generalize layer rules.	2019-12-17 11:03:36 -08:00
delay_data.py	Remove some flake8 errors/warnings.	2019-10-02 23:26:02 +00:00
design.py	Fix over-writing of active spacing rule.	2019-12-17 11:23:59 -08:00
geometry.py	Remove extra cast	2019-12-05 21:33:13 -08:00
graph_util.py	Made all cin function relate to farads and all input_load relate to relative units.	2019-08-08 01:57:04 -07:00
hierarchy_design.py	Allow gds to be written with supplies off. Fix extraction bug with new options.	2019-09-03 11:23:35 -07:00
hierarchy_layout.py	hierachy_layout: Move number of via arg to add_power_pins()	2019-12-18 17:33:43 +01:00
hierarchy_spice.py	Share nominal temperature and voltage. Nominal instead of typical.	2019-09-04 16:53:58 -07:00
lef.py	Added functionality to express polygons in LEF files.	2019-06-25 09:20:00 -07:00
pin_layout.py	Updates to gdsMill/tech layers	2019-12-04 16:12:53 -08:00
power_data.py	Move classes to individual file.	2019-07-16 15:18:04 -07:00
route.py	Fix space before comment	2019-06-14 08:43:41 -07:00
utils.py	Add layer-purpose GDS support. Various PEP8 fixes.	2019-11-14 18:17:20 +00:00
vector.py	Fix space before comment	2019-06-14 08:43:41 -07:00
verilog.py	Feedthru port edits.	2019-09-27 14:18:49 -07:00
wire.py	Fix space before comment	2019-06-14 08:43:41 -07:00
wire_path.py	Fix space before comment	2019-06-14 08:43:41 -07:00
wire_spice_model.py	Move classes to individual file.	2019-07-16 15:18:04 -07:00