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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-07 03:20:39 +02:00
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fa59b3d33dd692dcfb8b4073f6ae10bd4603387b
OpenRAM/technology/scn3me_subm/mag_lib
T
History
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2
2018-04-11 09:29:54 -07:00
..
cell_6t.gds
Mostly working for 1 bank.
2018-03-23 08:14:26 -07:00
cell_6t.mag
Mostly working for 1 bank.
2018-03-23 08:14:26 -07:00
dff.mag
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
ms_flop.mag
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
replica_cell_6t.mag
Mostly working for 1 bank.
2018-03-23 08:14:26 -07:00
sense_amp.mag
Move precharge and column mux cells to pgate directory.
2018-04-06 17:15:14 -07:00
tri_gate.mag
Fixed bug with missing tri gate via.
2018-01-29 17:29:30 -08:00
write_driver.mag
Change write driver supply pins to M2
2018-04-11 09:29:54 -07:00
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