jcirimel b18e2eae8d remove debug lines and merge

2021-02-09 20:53:23 -08:00

..

gds_lib

Rework bitcells.

2020-11-13 10:07:40 -08:00

mag_lib

Rework bitcells.

2020-11-13 10:07:40 -08:00

models

Adjusted vth0 of FF and SS models in scn4m from nominal.

2019-10-07 15:26:20 -07:00

sim_data

Updated sim_data for scmos

2021-01-22 00:51:14 -08:00

sp_lib

Rework bitcells.

2020-11-13 10:07:40 -08:00

tech

remove debug lines and merge

2021-02-09 20:53:23 -08:00

tf

Add draft lyt file -- connectivity not working

2020-08-14 10:38:22 -07:00

__init__.py

update copyright year.

2021-01-22 11:24:53 -08:00