mirror of https://github.com/VLSIDA/OpenRAM.git
235 lines
8.6 KiB
Markdown
235 lines
8.6 KiB
Markdown
# BASIC SETUP
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Please look at the OpenRAM ICCAD paper and presentation in the repository:
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https://github.com/mguthaus/OpenRAM/blob/master/OpenRAM_ICCAD_2016_paper.pdf
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https://github.com/mguthaus/OpenRAM/blob/master/OpenRAM_ICCAD_2016_presentation.pdf
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The OpenRAM compiler has very few dependencies:
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* ngspice-26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later)
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* Python 2.7 and higher (currently excludes Python 3 and up)
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* Python numpy
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* a setup script for each technology
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* a technology directory for each technology with the base cells
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If you want to perform DRC and LVS, you will need either:
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* Calibre (for FreePDK45 or SCMOS)
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* Magic + Netgen (for SCMOS only)
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You must set two environment variables: OPENRAM_HOME should point to
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the compiler source directory. OPENERAM_TECH should point to a root
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technology directory that contains subdirs of all other technologies.
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For example, in bash, add to your .bashrc:
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```
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export OPENRAM_HOME="$HOME/OpenRAM/compiler"
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export OPENRAM_TECH="$HOME/OpenRAM/technology"
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```
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For example, in csh/tcsh, add to your .cshrc/.tcshrc:
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```
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setenv OPENRAM_HOME "$HOME/OpenRAM/compiler"
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setenv OPENRAM_TECH "$HOME/OpenRAM/technology"
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```
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If you are using FreePDK, you should also have that set up and have the
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environment variable point to the PDK.
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For example, in bash, add to your .bashrc:
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```
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export FREEPDK45="/bsoe/software/design-kits/FreePDK45"
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```
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For example, in csh/tcsh, add to your .tcshrc:
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```
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setenv FREEPDK45 "/bsoe/software/design-kits/FreePDK45"
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```
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We do not distribute the PDK, but you may get it from:
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https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
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If you are using SCMOS, you should install Magic and netgen from:
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http://opencircuitdesign.com/magic/
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http://opencircuitdesign.com/netgen/
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In addition, you will need to install the MOSIS SCMOS rules for scn3me_subm
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that are part of QFlow:
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http://opencircuitdesign.com/qflow/
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# DIRECTORY STRUCTURE
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* compiler - openram compiler itself (pointed to by OPENRAM_HOME)
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* compiler/characterizer - timing characterization code
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* compiler/gdsMill - GDSII reader/writer
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* compiler/router - detailed router
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* compiler/tests - unit tests
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* technology - openram technology directory (pointed to by OPENRAM_TECH)
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* technology/freepdk45 - example configuration library for freepdk45 technology node
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* technology/scn3me_subm - example configuration library SCMOS technology node
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* technology/setup_scripts - setup scripts to customize your PDKs and OpenRAM technologies
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# UNIT TESTS
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Regression testing performs a number of tests for all modules in OpenRAM.
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Use the command:
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```
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python regress.py
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```
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To run a specific test:
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```
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python {unit test}.py
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```
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The unit tests take the same arguments as openram.py itself.
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To increase the verbosity of the test, add one (or more) -v options:
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```
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python tests/00_code_format_check_test.py -v -t freepdk45
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```
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To specify a particular technology use "-t <techname>" such as
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"-t scn3me_subm". The default for a unit test is freepdk45 whereas
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the default for openram.py is specified in the configuration file.
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A regression daemon script that can be used with cron is included in
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a separate repository at https://github.com/mguthaus/openram-daemons
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```
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regress_daemon.py
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regress_daemon.sh
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```
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This updates a git repository, checks out code, and sends an email
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report with status information.
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# CREATING CUSTOM TECHNOLOGIES
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All setup scripts should be in the setup_scripts directory under the
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$OPENRAM_TECH directory. Please look at the following file for an
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example of what is needed for OpenRAM:
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```
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$OPENRAM_TECH/setup_scripts/setup_openram_freepdk45.py
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```
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Each setup script should be named as: setup_openram_{tech name}.py.
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Each specific technology (e.g., freepdk45) should be a subdirectory
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(e.g., $OPENRAM_TECH/freepdk45) and include certain folders and files:
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1. gds_lib folder with all the .gds (premade) library cells. At a
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minimum this includes:
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* ms_flop.gds
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* sense_amp.gds
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* write_driver.gds
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* cell_6t.gds
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* replica_cell_6t.gds
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* tri_gate.gds
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2. sp_lib folder with all the .sp (premade) library netlists for the above cells.
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3. layers.map
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4. A valid tech Python module (tech directory with __init__.py and tech.py) with:
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* References in tech.py to spice models
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* DRC/LVS rules needed for dynamic cells and routing
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* Layer information
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* etc.
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# DEBUGGING
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When OpenRAM runs, it puts files in a temporary directory that is
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shown in the banner at the top. Like:
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```
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/tmp/openram_mrg_18128_temp/
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```
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This is where simulations and DRC/LVS get run so there is no network
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traffic. The directory name is unique for each person and run of
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OpenRAM to not clobber any files and allow simultaneous runs. If it
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passes, the files are deleted. If it fails, you will see these files:
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* temp.gds is the layout
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* (.mag files if using SCMOS)
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* temp.sp is the netlist
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* test1.drc.err is the std err output of the DRC command
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* test1.drc.out is the standard output of the DRC command
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* test1.drc.results is the DRC results file
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* test1.lvs.err is the std err output of the LVS command
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* test1.lvs.out is the standard output of the LVS command
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* test1.lvs.results is the DRC results file
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Depending on your DRC/LVS tools, there will also be:
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* _calibreDRC.rul_ is the DRC rule file (Calibre)
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* dc_runset is the command file (Calibre)
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* extracted.sp (Calibre)
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* run_lvs.sh is a Netgen script for LVS (Netgen)
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* run_drc.sh is a Magic script for DRC (Magic)
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* <topcell>.spice (Magic)
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If DRC/LVS fails, the first thing is to check if it ran in the .out and
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.err file. This shows the standard output and error output from
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running DRC/LVS. If there is a setup problem it will be shown here.
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If DRC/LVS runs, but doesn't pass, you then should look at the .results
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file. If the DRC fails, it will typically show you the command that was used
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to run Calibre or Magic+Netgen.
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To debug, you will need a layout viewer. I prefer to use Glade
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on my Mac, but you can also use Calibre, Magic, etc.
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1. Calibre
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Start the Calibre DESIGNrev viewer in the temp directory and load your GDS file:
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```
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calibredrv temp.gds
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```
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Select Verification->Start RVE and select the results database file in
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the new form (e.g., test1.drc.db). This will start the RVE (results
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viewer). Scroll through the check pane and find the DRC check with an
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error. Select it and it will open some numbers to the right. Double
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click on any of the errors in the result browser. These will be
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labelled as numbers "1 2 3 4" for example will be 4 DRC errors.
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In the viewer ">" opens the layout down a level.
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2. Glade
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You can view errors in Glade as well. I like this because it is on my laptop.
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You can get it from: http://www.peardrop.co.uk/glade/
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To remote display over X windows, you need to disable OpenGL acceleration or use vnc
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or something. You can disable by adding this to your .bashrc in bash:
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```
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export GLADE_USE_OPENGL=no
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```
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or in .cshrc/.tcshrc in csh/tcsh:
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```
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setenv GLADE_USE_OPENGAL no
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```
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To use this with the FreePDK45 or SCMOS layer views you should use the
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tech files. Then create a .glade.py file in your user directory with
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these commands to load the technology layers:
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```
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ui().importCds("default",
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"/Users/mrg/techfiles/freepdk45/display.drf",
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"/Users/mrg/techfiles/freepdk45/FreePDK45.tf", 1000, 1,
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"/Users/mrg/techfiles/freepdk45/layers.map")
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```
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Obviously, edit the paths to point to your directory. To switch
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between processes, you have to change the importCds command (or you
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can manually run the command each time you start glade).
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To load the errors, you simply do Verify->Import Calibre Errors select
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the .results file from Calibre.
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3. Magic
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Magic is only supported in SCMOS. You will need to install the MOSIS SCMOS rules
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and Magic from: http://opencircuitdesign.com/
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When running DRC or extraction, OpenRAM will load the GDS file, save
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the .ext/.mag files, and export an extracted netlist (.spice).
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4. It is possible to use other viewers as well, such as:
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* LayoutEditor http://www.layouteditor.net/
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# Example to output/input .gds layout files from/to Cadence
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1. To create your component layouts, you should stream them to
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individual gds files using our provided layermap and flatten
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cells. For example,
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```
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strmout -layerMap layers.map -library sram -topCell $i -view layout -flattenVias -flattenPcells -strmFile ../gds_lib/$i.gds
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```
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2. To stream a layout back into Cadence, do this:
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```
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strmin -layerMap layers.map -attachTechFileOfLib NCSU_TechLib_FreePDK45 -library sram_4_32 -strmFile sram_4_32.gds
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```
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When you import a gds file, make sure to attach the correct tech lib
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or you will get incorrect layers in the resulting library.
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