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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 09:58:33 +02:00
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f7915ec55e687adade51973fd22576563c2c3639
OpenRAM/technology/freepdk45/sp_lib
T
History
mrg ae9dbe203d Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
..
cell_1rw_1r.sp
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
cell_1w_1r.sp
Fix error in cell width. Fix escape warning.
2019-02-24 10:48:54 -08:00
cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
dff.sp
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
dummy_cell_1rw_1r.sp
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
dummy_cell_1w_1r.sp
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
dummy_cell_6t.sp
Add freepdk45 dummy cells
2019-07-03 14:53:44 -07:00
replica_cell_1rw_1r.sp
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
replica_cell_1w_1r.sp
Fix mising file
2019-02-24 11:04:56 -08:00
replica_cell_6t.sp
Modify replica cell spice in FreePDK45 to short Qbar to vdd
2018-11-05 11:42:42 -08:00
sense_amp.sp
…
tri_gate.sp
…
write_driver.sp
…
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