Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
f3f19aeeeb93e5e87f75056da9ba4ca539b140a3
OpenRAM/technology/scn4m_subm
T
History
Jesse Cirimelli-Low 8346ad736e add dimension contraints to other tech files
2021-06-18 14:36:15 -07:00
..
gds_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
mag_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sim_data
Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction.
2021-05-24 10:44:46 -07:00
sp_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
tech
add dimension contraints to other tech files
2021-06-18 14:36:15 -07:00
tf
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
__init__.py
update copyright year.
2021-01-22 11:24:53 -08:00
Powered by Gitea Version: 1.27.2 Page: 138ms Template: 6ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API