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OpenRAM
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OpenRAM/compiler/modules
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Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 		2018-05-14 16:15:45 -07:00
..
bank.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
bank_select.py Supply to M3 for bank select logic 2018-04-11 16:55:09 -07:00
bitcell.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
bitcell_array.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
control_logic.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
delay_chain.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
dff.py Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
dff_array.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
dff_buf.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
dff_buf_array.py Add M3 pins on dff_buf array 2018-04-11 12:09:15 -07:00
dff_inv.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
dff_inv_array.py Add bank_sel to bank_select module as input. 2018-03-23 08:13:39 -07:00
hierarchical_decoder.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
hierarchical_predecode.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
hierarchical_predecode2x4.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
hierarchical_predecode3x8.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
ms_flop.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
ms_flop_array.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
precharge_array.py Route precharge_array vdd in M3 2018-04-04 13:49:55 -07:00
replica_bitcell.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
replica_bitline.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
sense_amp.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
sense_amp_array.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
single_level_column_mux_array.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
tri_gate.py Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
tri_gate_array.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00
wordline_driver.py Move supply to M3 in wordline driver 2018-04-11 16:23:45 -07:00
write_driver.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
write_driver_array.py Convert entire OpenRAM to use python3. Works with Python 3.6. 2018-05-14 16:15:45 -07:00