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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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OpenRAM/compiler/pgates
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Matt Guthaus 2b7025335c Use pand2 of correct size. Simplify width checking of AND array.
2019-08-21 11:20:35 -07:00
..
pand2.py
Use pand2 of correct size. Simplify width checking of AND array.
2019-08-21 11:20:35 -07:00
pand3.py
Use pdriver instead of pinv in pand gates.
2019-08-21 10:18:46 -07:00
pbuf.py
Removed all unused analytical delay functions.
2019-08-06 17:09:25 -07:00
pdriver.py
Use pand2 of correct size. Simplify width checking of AND array.
2019-08-21 11:20:35 -07:00
pgate.py
…
pinv.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
pinvbuf.py
Removed all unused analytical delay functions.
2019-08-06 17:09:25 -07:00
pnand2.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
pnand3.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
pnor2.py
Merge branch 'dev' into analytical_cleanup
2019-08-08 13:20:27 -07:00
precharge.py
Add direction to pins of all modules
2019-08-06 14:14:09 -07:00
ptristate_inv.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
ptx.py
…
single_level_column_mux.py
Added graph functions to compute analytical delay based on graph path.
2019-08-07 01:50:48 -07:00
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