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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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f05865b307319f9c7c5bdacf5442d9cbdac50cce
OpenRAM/technology
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Hunter Nichols f05865b307 Fixed drc issues with replica bitline test.
2018-11-02 17:16:41 -07:00
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freepdk45
Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.
2018-11-01 12:29:49 -07:00
scn3me_subm
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
scn4m_subm
Fixed drc issues with replica bitline test.
2018-11-02 17:16:41 -07:00
setup_scripts
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
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