mirror of https://github.com/VLSIDA/OpenRAM.git
241 lines
10 KiB
Python
241 lines
10 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import sys
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from tech import drc, spice
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import debug
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from math import log,sqrt,ceil
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import datetime
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import getpass
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from vector import vector
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from globals import OPTS, print_time
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from sram_base import sram_base
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from bank import bank
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from dff_buf_array import dff_buf_array
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from dff_array import dff_array
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class sram_2bank(sram_base):
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"""
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Procedures specific to a two bank SRAM.
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"""
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def __init__(self, name, sram_config):
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sram_base.__init__(self, name, sram_config)
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def compute_bank_offsets(self):
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""" Compute the overall offsets for a two bank SRAM """
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# In 2 bank SRAM, the height is determined by the control bus which is higher than the msb address
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self.vertical_bus_height = self.bank.height + 2*self.bank_to_bus_distance + self.data_bus_height + self.control_bus_height
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# The address bus extends down through the power rails, but control and bank_sel bus don't
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self.addr_bus_height = self.vertical_bus_height
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self.vertical_bus_offset = vector(self.bank.width + self.bank_to_bus_distance, 0)
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self.data_bus_offset = vector(0, self.bank.height + self.bank_to_bus_distance)
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self.supply_bus_offset = vector(0, self.data_bus_offset.y + self.data_bus_height)
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self.control_bus_offset = vector(0, self.supply_bus_offset.y + self.supply_bus_height)
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self.bank_sel_bus_offset = self.vertical_bus_offset + vector(self.m2_pitch*self.control_size,0)
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self.addr_bus_offset = self.bank_sel_bus_offset.scale(1,0) + vector(self.m2_pitch*self.num_banks,0)
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# Control is placed at the top above the control bus and everything
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self.control_logic_position = vector(0, self.control_bus_offset.y + self.control_bus_height + self.m1_pitch)
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# Bank select flops get put to the right of control logic above bank1 and the buses
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# Leave a pitch to get the vdd rails up to M2
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self.msb_address_position = vector(self.bank_inst[1].lx() + 3*self.supply_rail_pitch,
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self.supply_bus_offset.y + self.supply_bus_height \
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+ 2*self.m1_pitch + self.msb_address.width)
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def add_modules(self):
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""" Adds the modules and the buses to the top level """
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self.compute_bus_sizes()
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self.add_banks()
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self.compute_bank_offsets()
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self.add_busses()
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self.add_logic()
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self.width = self.bank_inst[1].ur().x
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self.height = self.control_logic_inst.uy()
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def add_banks(self):
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# Placement of bank 0 (left)
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bank_position_0 = vector(self.bank.width,
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self.bank.height)
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self.bank_inst=[self.add_bank(0, bank_position_0, -1, -1)]
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# Placement of bank 1 (right)
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x_off = self.bank.width + self.vertical_bus_width + 2*self.bank_to_bus_distance
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bank_position_1 = vector(x_off, bank_position_0.y)
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self.bank_inst.append(self.add_bank(1, bank_position_1, -1, 1))
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def add_logic(self):
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""" Add the control and MSB logic """
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self.add_control_logic(position=self.control_logic_position)
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self.msb_address_inst = self.add_inst(name="msb_address",
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mod=self.msb_address,
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offset=self.msb_address_position,
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rotate=270)
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self.msb_bank_sel_addr = "addr[{}]".format(self.addr_size-1)
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self.connect_inst([self.msb_bank_sel_addr,"bank_sel[1]","bank_sel[0]","clk_buf", "vdd", "gnd"])
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def route_shared_banks(self):
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""" Route the shared signals for two and four bank configurations. """
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# create the input control pins
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for n in self.control_logic_inputs + ["clk"]:
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self.copy_layout_pin(self.control_logic_inst, n)
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# connect the control logic to the control bus
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for n in self.control_logic_outputs + ["vdd", "gnd"]:
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pins = self.control_logic_inst.get_pins(n)
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for pin in pins:
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if pin.layer=="m2":
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pin_pos = pin.bc()
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break
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rail_pos = vector(pin_pos.x,self.horz_control_bus_positions[n].y)
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self.add_path("m2",[pin_pos,rail_pos])
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self.add_via_center(self.m1_stack,rail_pos)
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# connect the control logic cross bar
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for n in self.control_logic_outputs:
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cross_pos = vector(self.vert_control_bus_positions[n].x,self.horz_control_bus_positions[n].y)
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self.add_via_center(self.m1_stack,cross_pos)
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# connect the bank select signals to the vertical bus
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for i in range(self.num_banks):
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pin = self.bank_inst[i].get_pin("bank_sel")
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pin_pos = pin.rc() if i==0 else pin.lc()
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rail_pos = vector(self.vert_control_bus_positions["bank_sel[{}]".format(i)].x,pin_pos.y)
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self.add_path("m3",[pin_pos,rail_pos])
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self.add_via_center(self.m2_stack,rail_pos)
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def route_single_msb_address(self):
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""" Route one MSB address bit for 2-bank SRAM """
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# connect the bank MSB flop supplies
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vdd_pins = self.msb_address_inst.get_pins("vdd")
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for vdd_pin in vdd_pins:
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if vdd_pin.layer != "m1": continue
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vdd_pos = vdd_pin.bc()
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down_pos = vdd_pos - vector(0,self.m1_pitch)
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rail_pos = vector(vdd_pos.x,self.horz_control_bus_positions["vdd"].y)
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self.add_path("m1",[vdd_pos,down_pos])
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self.add_via_center(self.m1_stack,down_pos,rotate=90)
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self.add_path("m2",[down_pos,rail_pos])
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self.add_via_center(self.m1_stack,rail_pos)
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gnd_pins = self.msb_address_inst.get_pins("gnd")
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# Only add the ground connection to the lowest metal2 rail in the flop array
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# FIXME: SCMOS doesn't have a vertical rail in the cell, or we could use those
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lowest_y = None
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for gnd_pin in gnd_pins:
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if gnd_pin.layer != "m2": continue
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if lowest_y==None or gnd_pin.by()<lowest_y:
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lowest_y=gnd_pin.by()
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gnd_pos = gnd_pin.ur()
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rail_pos = vector(gnd_pos.x,self.horz_control_bus_positions["gnd"].y)
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self.add_path("m2",[gnd_pos,rail_pos])
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self.add_via_center(self.m1_stack,rail_pos)
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# connect the MSB flop to the address input bus
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msb_pins = self.msb_address_inst.get_pins("din[0]")
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for msb_pin in msb_pins:
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if msb_pin.layer == "m3":
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msb_pin_pos = msb_pin.lc()
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break
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rail_pos = vector(self.vert_control_bus_positions[self.msb_bank_sel_addr].x,msb_pin_pos.y)
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self.add_path("m3",[msb_pin_pos,rail_pos])
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self.add_via_center(self.m2_stack,rail_pos)
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# Connect the output bar to select 0
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msb_out_pin = self.msb_address_inst.get_pin("dout_bar[0]")
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msb_out_pos = msb_out_pin.rc()
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out_extend_right_pos = msb_out_pos + vector(2*self.m2_pitch,0)
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out_extend_up_pos = out_extend_right_pos + vector(0,self.m2_width)
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rail_pos = vector(self.vert_control_bus_positions["bank_sel[0]"].x,out_extend_up_pos.y)
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self.add_path("m2",[msb_out_pos,out_extend_right_pos,out_extend_up_pos])
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self.add_wire(("m3","via2","m2"),[out_extend_right_pos,out_extend_up_pos,rail_pos])
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self.add_via_center(self.m2_stack,rail_pos)
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# Connect the output to select 1
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msb_out_pin = self.msb_address_inst.get_pin("dout[0]")
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msb_out_pos = msb_out_pin.rc()
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out_extend_right_pos = msb_out_pos + vector(2*self.m2_pitch,0)
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out_extend_down_pos = out_extend_right_pos - vector(0,2*self.m1_pitch)
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rail_pos = vector(self.vert_control_bus_positions["bank_sel[1]"].x,out_extend_down_pos.y)
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self.add_path("m2",[msb_out_pos,out_extend_right_pos,out_extend_down_pos])
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self.add_wire(("m3","via2","m2"),[out_extend_right_pos,out_extend_down_pos,rail_pos])
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self.add_via_center(self.m2_stack,rail_pos)
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# Connect clk
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clk_pin = self.msb_address_inst.get_pin("clk")
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clk_pos = clk_pin.bc()
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rail_pos = self.horz_control_bus_positions["clk_buf"]
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bend_pos = vector(clk_pos.x,self.horz_control_bus_positions["clk_buf"].y)
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self.add_path("m1",[clk_pos,bend_pos,rail_pos])
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def route(self):
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""" Route all of the signals for the two bank SRAM. """
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self.route_shared_banks()
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# connect the horizontal control bus to the vertical bus
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# connect the data output to the data bus
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for n in self.data_bus_names:
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for i in [0,1]:
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pin_pos = self.bank_inst[i].get_pin(n).uc()
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rail_pos = vector(pin_pos.x,self.data_bus_positions[n].y)
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self.add_path("m2",[pin_pos,rail_pos])
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self.add_via_center(self.m2_stack,rail_pos)
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self.route_single_msb_address()
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# connect the banks to the vertical address bus
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# connect the banks to the vertical control bus
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for n in self.addr_bus_names + self.control_bus_names:
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# Skip these from the horizontal bus
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if n in ["vdd", "gnd"]: continue
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# This will be the bank select, so skip it
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if n == self.msb_bank_sel_addr: continue
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pin0_pos = self.bank_inst[0].get_pin(n).rc()
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pin1_pos = self.bank_inst[1].get_pin(n).lc()
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rail_pos = vector(self.vert_control_bus_positions[n].x,pin0_pos.y)
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self.add_path("m3",[pin0_pos,pin1_pos])
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self.add_via_center(self.m2_stack,rail_pos)
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def add_lvs_correspondence_points(self):
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"""
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This adds some points for easier debugging if LVS goes wrong.
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These should probably be turned off by default though, since extraction
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will show these as ports in the extracted netlist.
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"""
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if self.num_banks==1: return
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for n in self.control_bus_names:
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self.add_label(text=n,
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layer="m2",
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offset=self.vert_control_bus_positions[n])
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for n in self.bank_sel_bus_names:
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self.add_label(text=n,
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layer="m2",
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offset=self.vert_control_bus_positions[n])
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