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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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ed2fa10caa908fb708ac5f604e2fff61c31bb065
OpenRAM/compiler/base
T
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Matt Guthaus ed2fa10caa Use LSB for column mux.
Detect via size for power ring.
2018-03-23 08:13:20 -07:00
..
contact.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
design.py
Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.
2018-03-23 08:13:20 -07:00
geometry.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
hierarchy_layout.py
Use LSB for column mux.
2018-03-23 08:13:20 -07:00
hierarchy_spice.py
Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.
2018-03-23 08:13:20 -07:00
lef.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
path.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
pin_layout.py
Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
2018-03-23 08:12:47 -07:00
route.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
utils.py
Move utils to base.
2018-02-09 10:42:23 -08:00
vector.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
verilog.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
wire.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
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