OpenRAM/compiler/pgates
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches.
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
2020-05-10 11:32:45 -07:00
..
pand2.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pand3.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pbuf.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pdriver.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pgate.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pinv.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pinvbuf.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
pnand2.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pnand3.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pnor2.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
precharge.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
ptristate_inv.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
ptx.py Changes to simplify metal preferred directions and pitches. 2020-05-10 11:32:45 -07:00
pwrite_driver.py Add boundary to all pgates 2020-04-21 15:21:57 -07:00
single_level_column_mux.py s8 col mux array 2020-04-22 16:22:34 -07:00