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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-03 00:53:28 +02:00
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e6d6680da1f62a6a5571fe576aa354041c347443
OpenRAM/technology/scn3me_subm/tech
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Matt Guthaus 9d1f31467e Move internal power to clock pin. Differentiate leakge power when CSb is high.
2018-02-23 12:21:32 -08:00
..
__init__.py
Remove dead code ptx_port.
2018-01-19 16:19:05 -08:00
calibreDRC_scn3me_subm.rul
Add back scn3me_subm rule files
2016-11-09 09:32:26 -08:00
calibreLVS_scn3me_subm.rul
Add back scn3me_subm rule files
2016-11-09 09:32:26 -08:00
tech.py
Move internal power to clock pin. Differentiate leakge power when CSb is high.
2018-02-23 12:21:32 -08:00
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