mirror of https://github.com/VLSIDA/OpenRAM.git
219 lines
9.4 KiB
Python
219 lines
9.4 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from math import log
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import design
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import contact
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from tech import drc
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import debug
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import math
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from vector import vector
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from sram_factory import factory
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from globals import OPTS
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import logical_effort
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class single_level_column_mux_array(design.design):
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"""
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Dynamically generated column mux array.
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Array of column mux to read the bitlines through the 6T.
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"""
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def __init__(self, name, columns, word_size, bitcell_bl="bl", bitcell_br="br"):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("cols: {0} word_size: {1} bl: {2} br: {3}".format(columns, word_size, bitcell_bl, bitcell_br))
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self.columns = columns
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self.word_size = word_size
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self.words_per_row = int(self.columns / self.word_size)
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_array()
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def create_layout(self):
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self.setup_layout_constants()
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self.place_array()
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self.add_routing()
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# Find the highest shapes to determine height before adding well
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highest = self.find_highest_coords()
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self.height = highest.y
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self.add_layout_pins()
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self.add_enclosure(self.mux_inst, "pwell")
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(self.columns):
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self.add_pin("bl_{}".format(i))
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self.add_pin("br_{}".format(i))
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for i in range(self.words_per_row):
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self.add_pin("sel_{}".format(i))
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for i in range(self.word_size):
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self.add_pin("bl_out_{}".format(i))
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self.add_pin("br_out_{}".format(i))
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self.add_pin("gnd")
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def add_modules(self):
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self.mux = factory.create(module_type="single_level_column_mux",
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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self.add_mod(self.mux)
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def setup_layout_constants(self):
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self.column_addr_size = num_of_inputs = int(self.words_per_row / 2)
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self.width = self.columns * self.mux.width
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# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
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# one extra route pitch is to space from the sense amp
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self.route_height = (self.words_per_row + 3)*self.m1_pitch
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def create_array(self):
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self.mux_inst = []
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# For every column, add a pass gate
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for col_num in range(self.columns):
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name = "XMUX{0}".format(col_num)
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self.mux_inst.append(self.add_inst(name=name,
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mod=self.mux))
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self.connect_inst(["bl_{}".format(col_num),
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"br_{}".format(col_num),
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"bl_out_{}".format(int(col_num/self.words_per_row)),
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"br_out_{}".format(int(col_num/self.words_per_row)),
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"sel_{}".format(col_num % self.words_per_row),
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"gnd"])
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def place_array(self):
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# For every column, add a pass gate
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for col_num in range(self.columns):
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name = "XMUX{0}".format(col_num)
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x_off = vector(col_num * self.mux.width, self.route_height)
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self.mux_inst[col_num].place(x_off)
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def add_layout_pins(self):
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""" Add the pins after we determine the height. """
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# For every column, add a pass gate
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for col_num in range(self.columns):
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mux_inst = self.mux_inst[col_num]
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offset = mux_inst.get_pin("bl").ll()
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self.add_layout_pin(text="bl_{}".format(col_num),
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layer="m2",
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offset=offset,
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height=self.height-offset.y)
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offset = mux_inst.get_pin("br").ll()
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self.add_layout_pin(text="br_{}".format(col_num),
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layer="m2",
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offset=offset,
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height=self.height-offset.y)
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for inst in self.mux_inst:
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self.copy_layout_pin(inst, "gnd")
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def add_routing(self):
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self.add_horizontal_input_rail()
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self.add_vertical_poly_rail()
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self.route_bitlines()
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def add_horizontal_input_rail(self):
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""" Create address input rails on M1 below the mux transistors """
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for j in range(self.words_per_row):
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offset = vector(0, self.route_height + (j-self.words_per_row)*self.m1_pitch)
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self.add_layout_pin(text="sel_{}".format(j),
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layer="m1",
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offset=offset,
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width=self.mux.width * self.columns)
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def add_vertical_poly_rail(self):
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""" Connect the poly to the address rails """
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# Offset to the first transistor gate in the pass gate
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for col in range(self.columns):
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# which select bit should this column connect to depends on the position in the word
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sel_index = col % self.words_per_row
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# Add the column x offset to find the right select bit
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gate_offset = self.mux_inst[col].get_pin("sel").bc()
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# height to connect the gate to the correct horizontal row
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sel_height = self.get_pin("sel_{}".format(sel_index)).by()
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# use the y offset from the sel pin and the x offset from the gate
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offset = vector(gate_offset.x,self.get_pin("sel_{}".format(sel_index)).cy())
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# Add the poly contact with a shift to account for the rotation
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self.add_via_center(layers=("m1", "contact", "poly"),
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offset=offset)
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self.add_path("poly", [offset, gate_offset])
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def route_bitlines(self):
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""" Connect the output bit-lines to form the appropriate width mux """
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for j in range(self.columns):
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bl_offset = self.mux_inst[j].get_pin("bl_out").bc()
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br_offset = self.mux_inst[j].get_pin("br_out").bc()
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bl_out_offset = bl_offset - vector(0,(self.words_per_row+1)*self.m1_pitch)
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br_out_offset = br_offset - vector(0,(self.words_per_row+2)*self.m1_pitch)
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bl_out_offset_end = bl_out_offset + vector(0,self.route_height)
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br_out_offset_end = br_out_offset + vector(0,self.route_height)
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if (j % self.words_per_row) == 0:
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# Create the metal1 to connect the n-way mux output from the pass gate
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# These will be located below the select lines. Yes, these are M2 width
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# to ensure vias are enclosed and M1 min width rules.
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width = self.m2_width + self.mux.width * (self.words_per_row - 1)
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self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width,0)])
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self.add_path("m1", [br_out_offset, br_out_offset+vector(width,0)])
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# Extend the bitline output rails and gnd downward on the first bit of each n-way mux
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self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j/self.words_per_row)),
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layer="m2",
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start=bl_out_offset,
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end=bl_out_offset_end)
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self.add_layout_pin_segment_center(text="br_out_{}".format(int(j/self.words_per_row)),
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layer="m2",
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start=br_out_offset,
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end=br_out_offset_end)
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# This via is on the right of the wire
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self.add_via_center(layers=self.m1_stack,
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offset=bl_out_offset)
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# This via is on the left of the wire
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self.add_via_center(layers=self.m1_stack,
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offset=br_out_offset)
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else:
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self.add_path("m2", [ bl_out_offset, bl_out_offset_end])
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self.add_path("m2", [ br_out_offset, br_out_offset_end])
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# This via is on the right of the wire
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self.add_via_center(layers=self.m1_stack,
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offset=bl_out_offset)
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# This via is on the left of the wire
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self.add_via_center(layers=self.m1_stack,
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offset=br_out_offset)
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the NMOS pass TX"""
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from tech import parameter
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#Bitcell drain load being used to estimate mux NMOS drain load
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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return drain_load
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