Jesse Cirimelli-Low 0cba6a6050 single port sky130 crba passing lvs

2023-08-30 20:59:02 -07:00

..

__init__.py

Verilog ROM model created for testing

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channel_route.py

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contact.py

Revert pin/net spice object work

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delay_data.py

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design.py

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errors.py

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geometry.py

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hierarchy_design.py

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hierarchy_layout.py

single port sky130 crba passing lvs

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hierarchy_spice.py

reapply commit c8a06a1 patch that was incorrectly reverted

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lef.py

Revert pin/net spice object work

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logical_effort.py

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pin_layout.py

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power_data.py

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rom_verilog.py

Fixed formatting on all files

2023-06-14 12:28:36 -07:00

route.py

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timing_graph.py

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utils.py

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vector3d.py

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vector.py

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verilog.py

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wire_path.py

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wire_spice_model.py

add fixme note for unit conversion

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wire.py

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