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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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e45e2f77c9e536f2a72151adeaff958e9a8a4d13
OpenRAM/technology/freepdk45/gds_lib
T
History
mrg 8081bea708 Shrink 70nm contacts to 65nm
2021-09-16 15:28:39 -07:00
..
cell_1rw.gds
Shrink 70nm contacts to 65nm
2021-09-16 15:28:39 -07:00
cell_2rw.gds
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
dff.gds
Shrink 70nm contacts to 65nm
2021-09-16 15:28:39 -07:00
dummy_cell_1rw.gds
Shrink 70nm contacts to 65nm
2021-09-16 15:28:39 -07:00
dummy_cell_2rw.gds
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
replica_cell_1rw.gds
Shrink 70nm contacts to 65nm
2021-09-16 15:28:39 -07:00
replica_cell_2rw.gds
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
sense_amp.gds
Shrink 70nm contacts to 65nm
2021-09-16 15:28:39 -07:00
tri_gate.gds
Move sense amp to tri gate routing to M3... not ideal.
2018-04-23 09:14:18 -07:00
write_driver.gds
Move write_driver din left to avoid control signal in spare columns.
2020-07-16 14:47:14 -07:00
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