Hunter Nichols b44f840814 Changed delay calculation to include wire resistance and wire capacitance. Added bitline r and c values.

2021-08-01 19:25:54 -07:00

..

bitcell_1port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

bitcell_2port.py

Added direction information functions to 2-port bitcell modules

2021-06-21 17:19:15 -07:00

bitcell_base.py

Changed delay calculation to include wire resistance and wire capacitance. Added bitline r and c values.

2021-08-01 19:25:54 -07:00

col_cap_bitcell_1port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

col_cap_bitcell_2port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

dummy_bitcell_1port.py

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2021-01-22 11:23:28 -08:00

dummy_bitcell_2port.py

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2021-01-22 11:23:28 -08:00

dummy_pbitcell.py

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2021-01-22 11:23:28 -08:00

pbitcell.py

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2021-01-22 11:23:28 -08:00

replica_bitcell_1port.py

Update copyright year.

2021-01-22 11:23:28 -08:00

replica_bitcell_2port.py

Added direction information functions to 2-port bitcell modules

2021-06-21 17:19:15 -07:00

replica_pbitcell.py

Update copyright year.

2021-01-22 11:23:28 -08:00

row_cap_bitcell_1port.py

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2021-01-22 11:23:28 -08:00

row_cap_bitcell_2port.py

Update copyright year.

2021-01-22 11:23:28 -08:00