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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-07 03:20:39 +02:00
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dc20bf9e114780390aef6b65b34f02f374ed0a66
OpenRAM/technology/scn4m_subm
T
History
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%.
2018-12-12 23:59:32 -08:00
..
gds_lib
Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
2018-11-14 11:00:37 -08:00
mag_lib
Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
2018-11-14 11:00:37 -08:00
models
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
sp_lib
Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
sue_lib
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech
Added checks for the bitline voltage at sense amp enable 50%.
2018-12-12 23:59:32 -08:00
tf
Supply router working except:
2018-09-18 12:57:39 -07:00
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