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luke
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OpenRAM
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2026-08-29 09:30:38 +02:00
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dbe8a7f1af7ffcc90a133cf73482ad0e02e1565e
OpenRAM
/
compiler
/
sram
T
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mrg
ec6f0f1873
Escape route to any side
2021-01-06 09:40:32 -08:00
..
sram_1bank.py
Escape route to any side
2021-01-06 09:40:32 -08:00
sram_2bank.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
sram_base.py
Don't add vias when placing dff array
2020-12-22 17:08:53 -08:00
sram_config.py
Refactor dynamic cell name to utilize base class
2020-11-03 13:18:46 -08:00
sram.py
Only write drc/lvs scripts if drc/lvs is enabled
2020-12-23 07:16:43 -08:00