OpenRAM/technology/sky130/tech
Jesse Cirimelli-Low 0cba6a6050 single port sky130 crba passing lvs 2023-08-30 20:59:02 -07:00
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__init__.py Update copyright year 2023-01-28 22:56:27 -08:00
sky130.lydrc Add initial sky130 LVS/DRC rules. 2021-12-17 10:27:13 -08:00
sky130.lylvs Add initial sky130 LVS/DRC rules. 2021-12-17 10:27:13 -08:00
tech.py single port sky130 crba passing lvs 2023-08-30 20:59:02 -07:00