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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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da721a677d69a44e42808da7867964ed99b14d76
OpenRAM/compiler/bitcells
T
History
mrg da721a677d Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
..
bitcell_1rw_1r.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
bitcell_1w_1r.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
bitcell_base.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
bitcell.py
Use bitcell_base for all bitcells. Fix missing setup_bitcell call
2020-11-02 17:00:15 -08:00
col_cap_bitcell_1rw_1r.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
dummy_bitcell_1rw_1r.py
Use bitcell_base for all bitcells. Fix missing setup_bitcell call
2020-11-02 17:00:15 -08:00
dummy_bitcell_1w_1r.py
Use bitcell_base for all bitcells. Fix missing setup_bitcell call
2020-11-02 17:00:15 -08:00
dummy_bitcell.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
dummy_pbitcell.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
pbitcell.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
replica_bitcell_1rw_1r.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
replica_bitcell_1w_1r.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
replica_bitcell.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
replica_pbitcell.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
row_cap_bitcell_1rw_1r.py
PR from mithro + other changable GDS file names
2020-11-02 16:00:16 -08:00
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