Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit		2018-05-22 14:16:51 -07:00
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pbitcell.py	adding read/write port functionality to the design. Now the bitcell can have read/write, write, and read ports all at once. Changed unit tests to accomodate different combinations of ports.	2018-05-10 09:38:02 -07:00
pgate.py	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.	2018-03-23 08:14:09 -07:00
pinv.py	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.	2018-03-23 08:14:09 -07:00
pinvbuf.py	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.	2018-03-23 08:14:09 -07:00
pnand2.py	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.	2018-03-23 08:14:09 -07:00
pnand3.py	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.	2018-03-23 08:14:09 -07:00
pnor2.py	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.	2018-03-23 08:14:09 -07:00
precharge.py	changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit	2018-05-22 14:16:51 -07:00
ptx.py	Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.	2018-03-23 08:14:09 -07:00
single_level_column_mux.py	changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit	2018-05-22 14:16:51 -07:00