mirror of https://github.com/VLSIDA/OpenRAM.git
152 lines
4.7 KiB
Markdown
152 lines
4.7 KiB
Markdown
### [Go Back](./index.md)
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# Hierarchical Design Modules
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This page of the documentation explains the hierarchical design modules of OpenRAM.
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## Table of Contents
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1. [Hierarchical Design Modules](#hierarchical-design-modules-1)
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2. [Bank](#bank)
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3. [Port Data](#port-data)
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4. [Port Address](#port-address)
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5. [Plain Bitcell Array](#plain-bitcell-array)
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6. [Variations of Bitcells Needed](#variations-of-bitcells-needed)
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7. [Replica Bitcell Array](#replica-bitcell-array)
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8. [1D Arrays](#1d-arrays)
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9. [2D Arrays](#2d-arrays)
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10. [Delay Line](#delay-line)
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11. [Hierarchical (Address) Decoder](#hierarchical-address-decoder)
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## Hierarchical Design Modules
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* Memory building blocks
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* SRAM, Bank, Control Logic, Decoders, Column Mux, Various arrays (DFF, drivers)
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* Can override every module with a custom one in the configuration file
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* Each module must:
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* Create netlist
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* Define inputs/outputs
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* Instantiate and connect sub-modules and cells
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* Create layout
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* Place and route itself
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* Route vdd/gnd to M3
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* (Optional) Run DRC/LVS
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* Analytically model timing and power
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## Bank
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<img align="right" height="180" src="../assets/images/design_modules/bank.png">
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* Encompasses everything except
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* Data and Address Flops
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* Control logic
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* Multi-bank logic
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* Arranges ports
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* Port 0 is left/bottom
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* Port 1 is right/top
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## Port Data
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* Encapsulates all of the datapath logic for a rw, w, or r port
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* Sense amplifiers (read types)
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* Write drivers (write types)
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* Column mux (if any)
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* Precharge (read or write type) (write to not destroy half selected cells in a row)
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* Also includes a precharge for the replica columns
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## Port Address
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* Encapsulates the row decoder and wordline driver for easier placement next to a bank
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* Each port will have its own port_address module
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## Plain Bitcell Array
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<img align="right" height="150" src="../assets/images/design_modules/bitcell_array.png">
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* 2D Array of bit cells
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* Each row alternately flips vertically
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* Assume bitcells tile
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* Boundary is determined by boundary layer in GDS
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* Word line must abut
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* Bit lines must abut
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## Variations of Bitcells Needed
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* Normal bitcell for data storage
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* Replica bitcell that is fixed to output a 0 value
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* Dummy bitcell with bitlines disconnected (purely for wordline load and lithography regularity)
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<img align="right" width=300 src="../assets/images/design_modules/replica_bitcell_array.png">
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## Replica Bitcell Array
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* Bitcells: B=regular, D=dummy, R=replica
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* Main bitcell array ( $\color{green}{\textrm{green}}$ )
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* Replica cols for each read port ( $\color{skyblue}{\textrm{blue}}$ ) on left or right (any number)
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* Dummy bitcells on the top, bottom, left, and right for lithography regularity ( $\color{red}{\textrm{red}}$ )
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* Replica columns activate two replica bitcells
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* $\color{blue}{\textrm{One}}$ driven by replica wordline
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* $\color{royalblue}{\textrm{Second}}$ driven by one of the normal wordlines (dark blue)
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* Second port word and bit lines not shown
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* Would be on right and top
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## 1D Arrays
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<img align="right" height="100" src="../assets/images/design_modules/1d_array.png">
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* Several modules have 1D arrays:
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* `sense_amp_array`
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* `write_driver_array`
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* `precharge_array`
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* `single_level_column_mux_array`
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* `tri_gate_array`
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* `wordline_driver` (*should change name to _array)
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* `sense_amp_array`, `write_driver_array`, `tri_gate_array` match column mux stride to space out
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* Wish list: Allow wide sense amplifier array to use multiple rows of sense amplifiers.
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<img align="right" height="250" src="../assets/images/design_modules/2d_array_vertical.png">
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## 2D Arrays
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* Regular DFF arrays (`dff_array.py`)
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* Buffered DFF arrays (`dff_buf_array.py`)
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* Inverted DFF array (`dff_inv_array.py`)
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* Can be $1*N$ or $N*1$ or $M*N$
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* Wish list: $M*N$ routes pins to edges
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<p align="center">
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<img align="center" height="80" src="../assets/images/design_modules/2d_array_horizontal.png">
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</p>
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## Delay Line
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<img align="right" height="200" src="../assets/images/design_modules/delay_line.png">
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* Configurable fanout and stages
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* `[4,4,4]` means 3 FO4 stages
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* `[1,1,4,4]` means 2 FO1 stages followed by FO4
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## Hierarchical (Address) Decoder
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<img align="right" height="200" src="../assets/images/design_modules/address_decoder.png">
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* Generic `hierarchical_predecode` class
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* Places routing rails and decode inverters
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* Derived to implement multiple predecoders
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* `hierarchical_predecode_2x4`
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* `hierarchical_predecode_3x8`
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* `hierarchical_predecode_4x16`
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* Hierarchical decoder uses predecoder + another decode stage
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* Predecoders are also used for the column mux decode and bank select decode
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* Wish list: Handle thin bitcell height |