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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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d82d3df4a717fe598956c801be91c75e39e4eae1
OpenRAM/compiler/characterizer
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Hunter Nichols d82d3df4a7 Added read port cycle data generation. This commit contains test code in create_test_cycles
2018-08-27 18:17:02 -07:00
..
__init__.py
Fix option reload problems and checkpointing so that it works properly.
2018-07-11 12:00:15 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Added read port cycle data generation. This commit contains test code in create_test_cycles
2018-08-27 18:17:02 -07:00
lib.py
Fixed timing to be measured from positive clock edge since
2018-07-26 13:58:50 -07:00
setup_hold.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
stimuli.py
Added basic structure to add_test_cycles to characterize multiple ports and its helper functions to allow for ports to be selected for characterization
2018-08-27 15:56:42 -07:00
trim_spice.py
Convert bitline index to integer in trim_spice
2018-07-26 14:29:44 -07:00
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