mirror of https://github.com/VLSIDA/OpenRAM.git
Allow trim netlist to be used for delay and functional simulation. Each class implements a "trim_insts" set of instances that can be removed. By default far left, right, top and bottom cells in the bitcell arrays are kept. Use lvs option in sp_write Fix lvs option in sram. |
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| .. | ||
| sram.py | ||
| sram_1bank.py | ||
| sram_2bank.py | ||
| sram_base.py | ||
| sram_config.py | ||