OpenRAM/compiler/sram
mrg d609e4ea04 Reimplement trim options (except on unit tests).
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
2021-04-07 16:07:56 -07:00
..
sram.py Reimplement trim options (except on unit tests). 2021-04-07 16:07:56 -07:00
sram_1bank.py Control logic route changes. 2021-03-24 14:32:10 -07:00
sram_2bank.py Update copyright year. 2021-01-22 11:23:28 -08:00
sram_base.py Reimplement trim options (except on unit tests). 2021-04-07 16:07:56 -07:00
sram_config.py Update copyright year. 2021-01-22 11:23:28 -08:00