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luke
/
OpenRAM
mirror of
https://github.com/VLSIDA/OpenRAM.git
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d51ec4fe45
OpenRAM
/
compiler
/
pgates
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mrg
6e2f60353c
Add wells to driver stages. Remove unnecessary height/center in control logic.
2021-03-25 10:00:24 -07:00
..
column_mux.py
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pand2.py
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pand3.py
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pand4.py
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pbuf.py
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pbuf_dec.py
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pdriver.py
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pgate.py
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pinv.py
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pinv_dec.py
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pinvbuf.py
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pnand2.py
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pnand3.py
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pnand4.py
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pnor2.py
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precharge.py
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ptristate_inv.py
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ptx.py
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pwrite_driver.py
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wordline_driver.py
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