mirror of https://github.com/VLSIDA/OpenRAM.git
62 lines
1.5 KiB
Verilog
62 lines
1.5 KiB
Verilog
// OpenRAM SRAM model
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// Words: 128
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// Word size: 8
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module sram_8_128_scn4m_subm(
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// Port 0: RW
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clk0,csb0,web0,addr0,din0,dout0
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);
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parameter DATA_WIDTH = 8 ;
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parameter ADDR_WIDTH = 7 ;
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parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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// FIXME: This delay is arbitrary.
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parameter DELAY = 3 ;
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input clk0; // clock
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input csb0; // active low chip select
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input web0; // active low write control
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input [ADDR_WIDTH-1:0] addr0;
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input [DATA_WIDTH-1:0] din0;
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output [DATA_WIDTH-1:0] dout0;
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reg csb0_reg;
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reg web0_reg;
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reg [ADDR_WIDTH-1:0] addr0_reg;
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reg [DATA_WIDTH-1:0] din0_reg;
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reg [DATA_WIDTH-1:0] dout0;
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// All inputs are registers
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always @(posedge clk0)
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begin
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csb0_reg = csb0;
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web0_reg = web0;
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addr0_reg = addr0;
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din0_reg = din0;
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dout0 = 8'bx;
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if ( !csb0_reg && web0_reg )
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$display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
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if ( !csb0_reg && !web0_reg )
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$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
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end
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reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
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// Memory Write Block Port 0
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// Write Operation : When web0 = 0, csb0 = 0
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always @ (negedge clk0)
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begin : MEM_WRITE0
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if ( !csb0_reg && !web0_reg )
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mem[addr0_reg] = din0_reg;
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end
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// Memory Read Block Port 0
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// Read Operation : When web0 = 1, csb0 = 0
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always @ (negedge clk0)
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begin : MEM_READ0
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if (!csb0_reg && web0_reg)
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dout0 <= #(DELAY) mem[addr0_reg];
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end
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endmodule
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