mirror of https://github.com/VLSIDA/OpenRAM.git
255 lines
10 KiB
Python
255 lines
10 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import pgate
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import debug
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from tech import drc, layer
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from vector import vector
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from sram_factory import factory
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from tech import cell_properties as cell_props
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from globals import OPTS
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class column_mux(pgate.pgate):
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"""
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This module implements the columnmux bitline cell used in the design.
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Creates a single column mux cell with the given integer size relative
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to minimum size. Default is 8x. Per Samira and Hodges-Jackson book:
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Column-mux transistors driven by the decoder must be sized
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for optimal speed
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"""
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def __init__(self, name, tx_size=8, bitcell_bl="bl", bitcell_br="br"):
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debug.info(2, "creating single column mux cell: {0}".format(name))
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self.tx_size = int(tx_size)
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self.bitcell_bl = bitcell_bl
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self.bitcell_br = bitcell_br
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super().__init__(name)
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def get_bl_names(self):
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return "bl"
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def get_br_names(self):
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return "br"
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def create_netlist(self):
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self.add_pins()
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self.add_ptx()
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def create_layout(self):
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# If li exists, use li and m1 for the mux, otherwise use m1 and m2
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if "li" in layer:
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self.col_mux_stack = self.li_stack
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else:
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self.col_mux_stack = self.m1_stack
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self.pin_layer = self.bitcell.get_pin(self.bitcell_bl).layer
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self.pin_pitch = getattr(self, "{}_pitch".format(self.pin_layer))
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self.pin_width = getattr(self, "{}_width".format(self.pin_layer))
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self.pin_height = 2 * self.pin_width
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self.place_ptx()
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cell = factory.create(module_type=OPTS.bitcell)
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if(cell_props.use_strap == True and OPTS.num_ports == 1):
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strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version)
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precharge_width = cell.width + strap.width
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else:
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precharge_width = cell.width
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self.width = precharge_width
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self.height = self.nmos_upper.uy() + self.pin_height
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self.connect_poly()
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self.add_bitline_pins()
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self.connect_bitlines()
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self.add_pn_wells()
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def add_ptx(self):
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self.bitcell = factory.create(module_type=OPTS.bitcell)
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# Adds nmos_lower,nmos_upper to the module
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self.ptx_width = self.tx_size * drc("minwidth_tx")
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self.nmos = factory.create(module_type="ptx",
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width=self.ptx_width)
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self.add_mod(self.nmos)
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# Space it in the center
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self.nmos_lower = self.add_inst(name="mux_tx1",
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mod=self.nmos)
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self.connect_inst(["bl", "sel", "bl_out", "gnd"])
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# This aligns it directly above the other tx with gates abutting
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self.nmos_upper = self.add_inst(name="mux_tx2",
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mod=self.nmos)
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self.connect_inst(["br", "sel", "br_out", "gnd"])
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def add_pins(self):
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self.add_pin_list(["bl", "br", "bl_out", "br_out", "sel", "gnd"])
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def add_bitline_pins(self):
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""" Add the top and bottom pins to this cell """
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bl_pos = vector(self.pin_pitch, 0)
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br_pos = vector(self.width - self.pin_pitch, 0)
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# bl and br
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self.add_layout_pin(text="bl",
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layer=self.pin_layer,
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offset=bl_pos + vector(0, self.height - self.pin_height),
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height=self.pin_height)
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self.add_layout_pin(text="br",
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layer=self.pin_layer,
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offset=br_pos + vector(0, self.height - self.pin_height),
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height=self.pin_height)
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# bl_out and br_out
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self.add_layout_pin(text="bl_out",
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layer=self.pin_layer,
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offset=bl_pos,
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height=self.pin_height)
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self.add_layout_pin(text="br_out",
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layer=self.pin_layer,
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offset=br_pos,
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height=self.pin_height)
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def place_ptx(self):
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""" Create the two pass gate NMOS transistors to switch the bitlines"""
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# Space it in the center
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nmos_lower_position = self.nmos.active_offset.scale(0, 1) \
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+ vector(0.5 * self.bitcell.width- 0.5 * self.nmos.active_width, 0)
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self.nmos_lower.place(nmos_lower_position)
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# This aligns it directly above the other tx with gates abutting
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nmos_upper_position = nmos_lower_position \
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+ vector(0, self.nmos.active_height + max(self.active_space, self.poly_space))
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self.nmos_upper.place(nmos_upper_position)
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if cell_props.pgate.add_implants:
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self.extend_implants()
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def connect_poly(self):
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""" Connect the poly gate of the two pass transistors """
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# offset is the top of the lower nmos' diffusion
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# height is the distance between the nmos' diffusions, which depends on max(self.active_space,self.poly_space)
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offset = self.nmos_lower.get_pin("G").ul() - vector(0, self.poly_extend_active)
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height = self.nmos_upper.get_pin("G").by() + self.poly_extend_active - offset.y
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self.add_rect(layer="poly",
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offset=offset,
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height=height)
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# Add the sel pin to the bottom of the mux
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self.add_layout_pin(text="sel",
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layer="poly",
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offset=self.nmos_lower.get_pin("G").ll(),
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height=self.poly_extend_active)
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def connect_bitlines(self):
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""" Connect the bitlines to the mux transistors """
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bl_pin = self.get_pin("bl")
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br_pin = self.get_pin("br")
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bl_out_pin = self.get_pin("bl_out")
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br_out_pin = self.get_pin("br_out")
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nmos_lower_s_pin = self.nmos_lower.get_pin("S")
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nmos_lower_d_pin = self.nmos_lower.get_pin("D")
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nmos_upper_s_pin = self.nmos_upper.get_pin("S")
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nmos_upper_d_pin = self.nmos_upper.get_pin("D")
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# Add vias to bl, br_out, nmos_upper/S, nmos_lower/D
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self.add_via_stack_center(from_layer=bl_pin.layer,
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to_layer=self.col_mux_stack[0],
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offset=bl_pin.bc())
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self.add_via_stack_center(from_layer=br_out_pin.layer,
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to_layer=self.col_mux_stack[0],
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offset=br_out_pin.uc())
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self.add_via_stack_center(from_layer=nmos_upper_s_pin.layer,
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to_layer=self.col_mux_stack[2],
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offset=nmos_upper_s_pin.center())
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self.add_via_stack_center(from_layer=nmos_lower_d_pin.layer,
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to_layer=self.col_mux_stack[2],
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offset=nmos_lower_d_pin.center())
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# bl -> nmos_upper/D on metal1
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# bl_out -> nmos_upper/S on metal2
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self.add_path(self.col_mux_stack[0],
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[bl_pin.ll(), vector(nmos_upper_d_pin.cx(), bl_pin.by()),
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nmos_upper_d_pin.center()])
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# halfway up, move over
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mid1 = bl_out_pin.uc().scale(1, 0.4) \
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+ nmos_upper_s_pin.bc().scale(0, 0.4)
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mid2 = bl_out_pin.uc().scale(0, 0.4) \
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+ nmos_upper_s_pin.bc().scale(1, 0.4)
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self.add_path(self.col_mux_stack[2],
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[bl_out_pin.uc(), mid1, mid2, nmos_upper_s_pin.center()])
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# br -> nmos_lower/D on metal2
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# br_out -> nmos_lower/S on metal1
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self.add_path(self.col_mux_stack[0],
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[br_out_pin.uc(),
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vector(nmos_lower_s_pin.cx(), br_out_pin.uy()),
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nmos_lower_s_pin.center()])
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# halfway up, move over
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mid1 = br_pin.bc().scale(1, 0.5) \
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+ nmos_lower_d_pin.uc().scale(0, 0.5)
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mid2 = br_pin.bc().scale(0, 0.5) \
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+ nmos_lower_d_pin.uc().scale(1, 0.5)
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self.add_path(self.col_mux_stack[2],
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[br_pin.bc(), mid1, mid2, nmos_lower_d_pin.center()])
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def extend_implants(self):
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"""
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Add top-to-bottom implants for adjacency issues in s8.
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"""
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# Route to the bottom
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ll = (self.nmos_lower.ll() - vector(2 * [self.implant_enclose_active])).scale(1, 0)
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# Don't route to the top
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ur = self.nmos_upper.ur() + vector(self.implant_enclose_active, 0)
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self.add_rect("nimplant",
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ll,
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ur.x - ll.x,
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ur.y - ll.y)
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def add_pn_wells(self):
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"""
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Add a well and implant over the whole cell. Also, add the
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pwell contact (if it exists)
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"""
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if(cell_props.use_strap == True and OPTS.num_ports == 1):
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strap = factory.create(module_type=cell_props.strap_module, version=cell_props.strap_version)
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rbc_width = self.bitcell.width + strap.width
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else:
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rbc_width = cell.width
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# Add it to the right, aligned in between the two tx
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active_pos = vector(rbc_width,
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self.nmos_upper.by() - 0.5 * self.poly_space)
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self.add_via_center(layers=self.active_stack,
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offset=active_pos,
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implant_type="p",
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well_type="p")
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# If there is a li layer, include it in the power stack
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self.add_via_center(layers=self.col_mux_stack,
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offset=active_pos)
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# Add the M1->..->power_grid_layer stack
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self.add_power_pin(name="gnd",
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loc=active_pos,
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start_layer="m1")
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# Add well enclosure over all the tx and contact
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if "pwell" in layer:
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self.add_rect(layer="pwell",
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offset=vector(0, 0),
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width=rbc_width,
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height=self.height)
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