7 Commits

Author	SHA1	Message	Date
Jesse Cirimelli-Low	64b1946d6e	sky130 singlebank drc clean	2021-05-03 12:52:07 -07:00
Jesse Cirimelli-Low	3a3da9e0d7	56 drc errors on col mux 1port	2021-05-02 21:49:09 -07:00
Matt Guthaus	30fc81a1f0	Update copyright year.	2021-01-22 11:23:28 -08:00
mrg	493c9125f1	Read different modules overrides for different num ports	2020-11-06 11:09:50 -08:00
mrg	da721a677d	Remove EOL whitespace globally	2020-11-03 06:29:17 -08:00
mrg	acfec369d6	Add ptx cell properties	2020-10-28 09:54:15 -07:00
mrg	c06b02e6fc	Rename single_level_column_mux to just column_mux	2020-10-05 08:56:51 -07:00