OpenRAM/compiler/modules
Hunter Nichols d0e6dc9ce7 First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
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bank.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
bitcell.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
bitcell_array.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
control_logic.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
delay_chain.py Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name. 2018-02-13 15:54:50 -08:00
hierarchical_decoder.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
hierarchical_predecode.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
hierarchical_predecode2x4.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
hierarchical_predecode3x8.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
ms_flop.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
ms_flop_array.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
precharge.py Fix typo in precharge. 2018-02-12 15:34:01 -08:00
precharge_array.py Change precharge input from clk to en 2018-02-12 15:32:47 -08:00
replica_bitcell.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
replica_bitline.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
sense_amp.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
sense_amp_array.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
single_level_column_mux.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
single_level_column_mux_array.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
tri_gate.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
tri_gate_array.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
wordline_driver.py First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level. 2018-02-26 16:32:28 -08:00
write_driver.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
write_driver_array.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00