This website requires JavaScript.
Explore
Help
Sign In
luke
/
OpenRAM
Watch
1
Star
0
Fork
0
mirror of
https://github.com/VLSIDA/OpenRAM.git
synced
2026-08-29 17:39:02 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
cf63499e769d3b3f9174f2d47a73aeb40e21d55c
OpenRAM
/
technology
/
freepdk45
/
tech
T
History
mrg
cf63499e76
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
..
__init__.py
Fix space before comment
2019-06-14 08:43:41 -07:00
tech.py
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
