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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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ce5001e0afba51d0272ec60b8091ee01c0185f13
OpenRAM/technology/freepdk45
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Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
..
gds_lib
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sp_lib
Added custom 1rw+1r bitcell. Testing are currently failing.
2018-10-22 17:02:21 -07:00
tech
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
tf
Add display techfiles from NCSU PDKs.
2018-03-02 10:30:03 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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