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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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cd987479b875298a31d907a66a5bc6372f446c1d
OpenRAM/compiler/verify
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Matt Guthaus 7ead566154 Remove cell rename during DRC. Keep flatten.
2018-09-05 16:00:48 -07:00
..
__init__.py
Add parameters to give preference to DRC/LVS/PEX tools like we do for spice.
2018-08-28 13:41:26 -07:00
assura.py
Add DRC/LVS/PEX statistics in verbose=1 mode
2018-07-11 11:59:24 -07:00
calibre.py
Add temporary options to LVS to allow name merging
2018-07-18 15:10:29 -07:00
magic.py
Remove cell rename during DRC. Keep flatten.
2018-09-05 16:00:48 -07:00
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