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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-31 18:25:18 +02:00
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cd339ebbd0d3b5f7be99ebc842524ca3e16cdaa5
OpenRAM
/
technology
/
freepdk45
/
sp_lib
T
History
ota2
15e57d89ca
fix end subckt typo
2021-02-27 18:28:07 -05:00
..
cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
dff.sp
…
dummy_cell_1rw.sp
fix end subckt typo
2021-02-27 18:28:07 -05:00
dummy_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
replica_cell_1rw.sp
Rework bitcells.
2020-11-13 10:07:40 -08:00
replica_cell_2rw.sp
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
sense_amp.sp
…
tri_gate.sp
…
write_driver.sp
…