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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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cbf9c4850409a2fab1dbc66ece1078bf2cd8b0ed
OpenRAM/compiler/router
T
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mrg cbf9c48504 Names in skiptests changed. Reduce grid router verbosity.
2020-10-23 09:22:59 -07:00
..
tests
Fix space before comment
2019-06-14 08:43:41 -07:00
direction.py
Fix space before comment
2019-06-14 08:43:41 -07:00
grid_cell.py
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
grid_path.py
Fix space before comment
2019-06-14 08:43:41 -07:00
grid_utils.py
Fix space before comment
2019-06-14 08:43:41 -07:00
grid.py
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
pin_group.py
Names in skiptests changed. Reduce grid router verbosity.
2020-10-23 09:22:59 -07:00
router_tech.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
router.py
Names in skiptests changed. Reduce grid router verbosity.
2020-10-23 09:22:59 -07:00
signal_grid.py
Fix space before comment
2019-06-14 08:43:41 -07:00
signal_router.py
Fix space before comment
2019-06-14 08:43:41 -07:00
supply_grid_router.py
Changes to allow decoder height to be a 2x multiple of bitcell height.
2020-05-10 06:56:22 -07:00
supply_grid.py
Fix space before comment
2019-06-14 08:43:41 -07:00
supply_tree_router.py
Starting single layer power router.
2019-06-03 15:28:55 -07:00
vector3d.py
vector: Implement hash cache for vector3d and vector
2020-01-03 12:16:10 +01:00
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