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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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c96a6d0b9d9d7d5d5461b11592fac0ad2a2feaee
OpenRAM/compiler/pgates
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mrg c96a6d0b9d Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
..
pand2.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pand3.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pbuf.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pdriver.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pgate.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pinv.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pinvbuf.py
Add boundary to all pgates
2020-04-21 15:21:57 -07:00
pnand2.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pnand3.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
pnor2.py
Add no well option. Add stack gates vertical option.
2020-05-11 16:22:08 -07:00
precharge.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
ptristate_inv.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
ptx.py
Changes to simplify metal preferred directions and pitches.
2020-05-10 11:32:45 -07:00
pwrite_driver.py
Add boundary to all pgates
2020-04-21 15:21:57 -07:00
single_level_column_mux.py
s8 col mux array
2020-04-22 16:22:34 -07:00
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