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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 01:24:39 +02:00
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c613693399f49cf63d3ec6a254b37f1692b66a76
OpenRAM
/
technology
/
scn4m_subm
T
History
Eren Dogan
96e57507bf
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
..
gds_lib
Move power pins to horizontal or vertical layer in all cells.
2022-03-31 16:36:19 -07:00
mag_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sim_data
Added more data for regression modules.
2021-06-21 17:21:00 -07:00
sp_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
tech
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
tf
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
__init__.py
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
